radiance · Radiance self-hosting compiler

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lib/std/arch/rv64/isel.rad 52.6 KiB raw
//! RV64 instruction selection.
//!
//! Walks IL and selects RV64 instructions for each operation.
//!
//! *Register resolution hierarchy*
//!
//!   getReg(ssa) -> Reg
//!     Primitive physical register lookup. Panics if the register is spilled.
//!     Used as a building block by the functions below.
//!
//!   getSrcReg(ssa, scratch) -> Reg
//!     Source register for an [`il::Reg`] operand. Returns the physical register,
//!     or loads a spilled value into `scratch`. Used for instruction fields
//!     typed as [`il::Reg`] (e.g. base addresses in Load/Store/Blit).
//!
//!   getDstReg(ssa, scratch) -> Reg
//!     Destination register for an instruction result. Returns the physical
//!     register, or records a pending spill and returns `scratch`. The pending
//!     spill is flushed by [`selectBlock`] after each instruction.
//!
//!   resolveVal(scratch, val) -> Reg
//!     Resolve an [`il::Val`] to whatever register holds it. Delegates to [`getSrcReg`]
//!     for register values; materializes immediates and symbols into `scratch`.
//!     Used for operands that can be consumed from any register.
//!
//!   loadVal(rd, val) -> Reg
//!     Force an [`il::Val`] into a specific register `rd`. Built on [`resolveVal`] + [`emitMv`].
//!     Used when the instruction requires the value in `rd` (e.g. `sub rd, rd, rs2`).

use std::mem;
use std::lang::il;
use std::lang::gen;
use std::lang::gen::regalloc;
use std::lang::gen::labels;

use super::encode;
use super::emit;

///////////////
// Constants //
///////////////

/// Shift amount for byte sign/zero extension.
constant SHIFT_W8: i32 = 64 - 8;
/// Shift amount for halfword sign/zero extension.
constant SHIFT_W16: i32 = 64 - 16;
/// Shift amount for word sign/zero extension.
constant SHIFT_W32: i32 = 64 - 32;
/// Mask for extracting byte value.
constant MASK_W8: i32 = 0xFF;
/// Maximum number of block arguments supported.
constant MAX_BLOCK_ARGS: u32 = 16;

/// Signed integer range limits.
constant I8_MIN: i64 = -128;
constant I8_MAX: i64 = 127;
constant I16_MIN: i64 = -32768;
constant I16_MAX: i64 = 32767;
constant I32_MIN: i64 = -2147483648;
constant I32_MAX: i64 = 2147483647;

/// Unsigned integer range limits.
constant U8_MAX: i64 = 255;
constant U16_MAX: i64 = 65535;
constant U32_MAX: i64 = 4294967295;

/// Binary operation.
union BinOp: Copy { Add, And, Or, Xor }
/// Shift operation.
union ShiftOp: Copy { Sll, Srl, Sra }
/// Compare operation.
union CmpOp: Copy { Slt, Ult }

/// A pending spill store to be flushed after instruction selection.
record PendingSpill: Copy {
    /// The SSA register that was spilled.
    ssa: il::Reg,
    /// The physical register holding the value to store.
    rd: gen::Reg,
}

////////////////////
// Selector State //
////////////////////

/// Instruction selector state.
export record Selector: 'scratch + 'selection where 'scratch: 'selection {
    /// Emitter for outputting instructions.
    e: &'selection mut emit::Emitter,
    /// Register allocation result.
    ralloc: &'selection regalloc::AllocResult 'scratch,
    /// Total stack frame size.
    frameSize: i32,
    /// Running offset into the reserve region of the frame.
    /// Tracks current position within the pre-allocated reserve slots.
    reserveOffset: i32,
    /// Pending spill store, auto-committed after each instruction.
    pendingSpill: ?PendingSpill,
    /// Next synthetic block index for skip-branch targets.
    nextSynthBlock: u32,
    /// Whether dynamic allocations exist.
    isDynamic: bool,
}

/////////////////////////
// Register Allocation //
/////////////////////////

/// Get the physical register for an already-allocated SSA register.
fn getReg 'scratch 'selection (s: &Selector 'scratch 'selection, ssa: il::Reg) -> gen::Reg where 'scratch: 'selection {
    let phys = s.ralloc.assignments[ssa.n] else {
        panic "getReg: spilled register has no physical assignment";
    };
    return phys;
}

/// Compute the offset for a spill slot.
/// When using FP (dynamic): offset from FP = `slot - totalSize`.
/// When using SP: offset from SP = `slot`.
fn spillOffset 'scratch 'selection (s: &Selector 'scratch 'selection, slot: i32) -> i32 where 'scratch: 'selection {
    if s.isDynamic {
        return slot - s.frameSize;
    }
    return slot;
}

/// Get the base register for spill slot addressing (FP or SP).
fn spillBase 'scratch 'selection (s: &Selector 'scratch 'selection) -> gen::Reg where 'scratch: 'selection {
    if s.isDynamic {
        return super::FP;
    }
    return super::SP;
}

/// Get the destination register for an SSA register.
/// If the register is spilled, records a pending spill and returns the scratch
/// register. The pending spill is auto-committed by [`selectBlock`] after each
/// instruction. If not spilled, returns the physical register.
fn getDstReg 'scratch 'selection (s: &mut Selector 'scratch 'selection, ssa: il::Reg, scratch: gen::Reg) -> gen::Reg where 'scratch: 'selection {
    if let _ = regalloc::spill::spillSlot(&s.ralloc.spill, ssa) {
        set s.pendingSpill = PendingSpill { ssa, rd: scratch };
        return scratch;
    }
    return getReg(s, ssa);
}

/// Get the source register for an SSA register.
/// If the register is spilled, loads the value from the spill slot into the
/// scratch register and returns it. Otherwise returns the physical register.
fn getSrcReg 'scratch 'selection (s: &mut Selector 'scratch 'selection, ssa: il::Reg, scratch: gen::Reg) -> gen::Reg where 'scratch: 'selection {
    if let slot = regalloc::spill::spillSlot(&s.ralloc.spill, ssa) {
        emit::emitLd(s.e, scratch, spillBase(s), spillOffset(s, slot));
        return scratch;
    }
    return getReg(s, ssa);
}

/// Resolve an IL value to the physical register holding it.
/// For non-spilled register values, returns the physical register directly.
/// For immediates, symbols, and spilled registers, materializes into `scratch`.
fn resolveVal 'scratch 'selection (s: &mut Selector 'scratch 'selection, scratch: gen::Reg, val: il::Val) -> gen::Reg where 'scratch: 'selection {
    match val {
        case il::Val::Reg(r) => {
            return getSrcReg(s, r, scratch);
        },
        case il::Val::Imm(imm) => {
            if imm == 0 {
                return super::ZERO;
            }
            emit::loadImm(s.e, scratch, imm);
            return scratch;
        },
        case il::Val::DataSym(name) => {
            emit::recordDataAddrLoad(s.e, name, scratch);
            return scratch;
        },
        case il::Val::FnAddr(name) => {
            emit::recordAddrLoad(s.e, name, scratch);
            return scratch;
        },
        case il::Val::Undef => {
            return scratch;
        }
    }
}

/// Load an IL value into a specific physical register.
/// Like [`resolveVal`], but ensures the value ends up in `rd`.
fn loadVal 'scratch 'selection (s: &mut Selector 'scratch 'selection, rd: gen::Reg, val: il::Val) -> gen::Reg where 'scratch: 'selection {
    let rs = resolveVal(s, rd, val);
    emitMv(s, rd, rs);
    return rd;
}

/// Emit a move instruction if source and destination differ.
fn emitMv 'scratch 'selection (s: &mut Selector 'scratch 'selection, rd: gen::Reg, rs: gen::Reg) where 'scratch: 'selection {
    if *rd <> *rs {
        emit::emit(s.e, encode::mv(rd, rs));
    }
}

/// Emit zero-extension from a sub-word type to the full register width.
fn emitZext(e: &mut emit::Emitter, rd: gen::Reg, rs: gen::Reg, typ: il::Type) {
    match typ {
        case il::Type::W8 => emit::emit(e, encode::andi(rd, rs, MASK_W8)),
        case il::Type::W16 => {
            emit::emit(e, encode::slli(rd, rs, SHIFT_W16));
            emit::emit(e, encode::srli(rd, rd, SHIFT_W16));
        },
        case il::Type::W32 => {
            emit::emit(e, encode::slli(rd, rs, SHIFT_W32));
            emit::emit(e, encode::srli(rd, rd, SHIFT_W32));
        },
        case il::Type::W64 => {}
    }
}

/// Emit sign-extension from a sub-word type to the full register width.
fn emitSext(e: &mut emit::Emitter, rd: gen::Reg, rs: gen::Reg, typ: il::Type) {
    match typ {
        case il::Type::W8 => {
            emit::emit(e, encode::slli(rd, rs, SHIFT_W8));
            emit::emit(e, encode::srai(rd, rd, SHIFT_W8));
        },
        case il::Type::W16 => {
            emit::emit(e, encode::slli(rd, rs, SHIFT_W16));
            emit::emit(e, encode::srai(rd, rd, SHIFT_W16));
        },
        case il::Type::W32 => {
            emit::emit(e, encode::addiw(rd, rs, 0));
        },
        case il::Type::W64 => {}
    }
}

/// Resolve a divisor in its declared width, trap if it becomes zero, and
/// return the canonicalized register.
fn resolveAndTrapIfZero 'scratch 'selection (
    s: &mut Selector 'scratch 'selection,
    b: il::Val,
    typ: il::Type,
    signed: bool
) -> gen::Reg where 'scratch: 'selection {
    let mut divisor = b;
    if let case il::Val::Imm(imm) = b {
        set divisor = il::Val::Imm(canonicalCmpImm(imm, typ, signed));
    }
    let rs2 = resolveVal(s, super::SCRATCH2, divisor);
    if not isExtendedImm(divisor, typ, signed) {
        emitCmpExt(s.e, rs2, rs2, typ, signed);
    }
    let mut knownNonZero = false;
    if let case il::Val::Imm(imm) = divisor {
        set knownNonZero = imm <> 0;
    }
    if not knownNonZero {
        emit::emit(s.e, encode::bne(rs2, super::ZERO, super::INSTR_SIZE * 2));
        emit::emit(s.e, encode::ebreak());
    }
    return rs2;
}

////////////////////////
// Instruction Select //
////////////////////////

/// Pre-scan result for reserve analysis.
record ReserveInfo: Copy {
    /// Total size needed for constant-sized reserves.
    size: i32,
    /// Whether any dynamic-sized reserves exist.
    isDynamic: bool,
}

/// Add a block's reserve instructions to the accumulated frame requirements.
/// Returns the total size needed for all static reserves, respecting alignment.
fn computeReserveInfo 'view (instrs: &[il::published::Instruction 'view], previous: ReserveInfo) -> ?ReserveInfo {
    let mut offset = previous.size;
    let mut isDynamic = previous.isDynamic;
    for instr in instrs {
        let case il::published::Code::Fixed(fixed) = il::published::code(&instr) else continue;
        match fixed {
            case il::Instr::Reserve { size, alignment, .. } => {
                if let case il::Val::Imm(sz) = size {
                    if alignment == 0 or (alignment & (alignment - 1)) <> 0 or sz < 0 {
                        return nil;
                    }
                    let aligned = (offset as u64 + alignment as u64 - 1) & ~(alignment as u64 - 1);
                    if aligned > 0x7fff0000 or sz as u64 > 0x7fff0000 - aligned {
                        return nil;
                    }
                    set offset = (aligned + sz as u64) as i32;
                } else {
                    set isDynamic = true;
                }
            },
            else => {},
        }
    }
    return ReserveInfo { size: offset, isDynamic };
}

/// Select instructions from published IL and its register assignments.
export fn selectFn 'input 'scratch (
    e: &mut emit::Emitter,
    ralloc: &regalloc::AllocResult 'scratch,
    view: &il::published::Function 'input
) {
    if e.error <> nil {
        return;
    }
    // Reset block offsets for this function.
    labels::resetBlocks(&mut e.labels);
    // Pre-scan for constant-sized reserves to promote to fixed frame slots.
    let mut reserveInfo = ReserveInfo { size: 0, isDynamic: false };
    for block in view.blocks {
        let next = computeReserveInfo(block.instructions, reserveInfo) else {
            set e.error = super::Error::Capacity;
            return;
        };
        set reserveInfo = next;
    }
    if reserveInfo.size as u64 + ralloc.spill.frameSize as u64 > 0x7fffff00 {
        set e.error = super::Error::Capacity; return;
    }
    let isLeaf = view.isLeaf;
    // Compute frame layout from spill slots, reserve slots, and used callee-saved registers.
    let frame = emit::computeFrame(
        ralloc.spill.frameSize + reserveInfo.size,
        ralloc.usedCalleeSaved,
        view.blocks.len,
        isLeaf,
        reserveInfo.isDynamic
    );
    // Synthetic block indices start after real blocks and the epilogue block.
    let resultRef: 'selection = &*ralloc, emitterRef = &mut *e where 'scratch: 'selection in {
        let mut s = Selector 'scratch 'selection {
            e: emitterRef,
            ralloc: resultRef,
            frameSize: frame.totalSize,
            reserveOffset: 0, pendingSpill: nil,
            nextSynthBlock: view.blocks.len + 1,
            isDynamic: frame.isDynamic,
        };
        // Record function name for printing.
        emit::recordFunc(s.e, view.name);
        // Record function code offset for call patching.
        emit::recordFuncOffset(s.e, view.name);
        // Emit prologue.
        emit::emitPrologue(s.e, &frame);

        // Move function params from arg registers to assigned registers.
        // Cross-call params may have been assigned to callee-saved registers
        // instead of their natural arg registers. Spilled params are stored
        // directly to their spill slots.
        for funcParam, i in view.params {
            if i < super::ARG_REGS.len {
                let param = funcParam.value;
                let argReg = super::ARG_REGS[i];

                if let slot = regalloc::spill::spillSlot(&ralloc.spill, param) {
                    // Spilled parameter: store arg register to spill slot.
                    emit::emitSd(s.e, argReg, spillBase(&s), spillOffset(&s, slot));
                } else if let assigned = ralloc.assignments[param.n] {
                    emitMv(&mut s, assigned, argReg);
                }
            }
        }

        // Emit each block.
        for i in 0..view.blocks.len {
            if s.e.error <> nil {
                return;
            }
            selectBlock(&mut s, i, &frame, view);
        }
        // Emit epilogue.
        emit::emitEpilogue(s.e, &frame);
        // Patch local branches now that all blocks are emitted.
        emit::patchLocalBranches(s.e);
    }
}

/// Select instructions for a block.
fn selectBlock 'input 'scratch 'selection (s: &mut Selector 'scratch 'selection, blockIdx: u32, frame: &emit::Frame, view: &il::published::Function 'input) where 'scratch: 'selection {
    // Record block address for branch patching.
    emit::recordBlock(s.e, blockIdx);

    // Block parameters are handled at jump sites (in `Jmp`/`Br`).
    // By the time we enter the block, the arguments have already been
    // moved to the parameter registers by the predecessor's terminator.

    // Process each instruction, auto-committing any pending spill after each.
    let locations = view.blocks[blockIdx].locations;
    let hasLocs = locations.len > 0;
    for instr, i in view.blocks[blockIdx].instructions {
        if s.e.error <> nil {
            return;
        }
        // Record debug location before emitting machine instructions.
        if hasLocs {
            emit::recordSrcLoc(s.e, locations[i]);
        }
        set s.pendingSpill = nil;
        let code = il::published::code(&instr);
        selectInstr(s, blockIdx, code, frame, view);

        // Flush the pending spill store, if any.
        if let p = s.pendingSpill {
            if let slot = regalloc::spill::spillSlot(&s.ralloc.spill, p.ssa) {
                emit::emitSd(s.e, p.rd, spillBase(s), spillOffset(s, slot));
            }
            set s.pendingSpill = nil;
        }
    }
}

/// Select instructions for a single IL instruction.
fn selectInstr 'input 'scratch 'selection (s: &mut Selector 'scratch 'selection, blockIdx: u32, instr: &il::published::Code 'input, frame: &emit::Frame, view: &il::published::Function 'input) where 'scratch: 'selection {
    match *instr {
        case il::published::Code::Jmp { target, args } => {
            selectJump(s, blockIdx, target, view.blocks[target].params, args);
        },
        case il::published::Code::Br { thenTarget, thenArgs, elseTarget, elseArgs, .. } => {
            let params: &'input [il::Param] = view.blocks[thenTarget].params
                if thenArgs.len > 0 and elseArgs.len == 0
                else view.blocks[elseTarget].params if elseArgs.len > 0 and thenArgs.len == 0
                else &view.params[..0];
            selectBranch(s, blockIdx, instr, params, thenArgs, elseArgs);
        },
        case il::published::Code::Switch { val, defaultTarget, defaultArgs, cases } => {
            let rs1 = resolveVal(s, super::SCRATCH1, val);
            for c in cases {
                let params: &'input [il::Param] = view.blocks[c.target].params
                    if c.args.len > 0 else &view.params[..0];
                selectSwitchCase(s, rs1, c.value, c.target, params, c.args);
            }
            // Fall through to default.
            emitBlockArgs(s, view.blocks[defaultTarget].params, defaultArgs);
            emit::recordBranch(s.e, defaultTarget, emit::BranchKind::Jump);
        },
        case il::published::Code::Call { dst, func, args, .. } => selectCall(s, &func, args, dst),
        case il::published::Code::Fixed(fixed) => selectFixedInstr(s, blockIdx, &fixed, frame),
    }
}

/// Compare one switch case and emit its argument moves only on a match.
fn selectSwitchCase 'scratch 'selection (
    s: &mut Selector 'scratch 'selection,
    rs1: gen::Reg,
    value: i64,
    target: u32,
    params: &[il::Param],
    args: &[il::Val]
) where 'scratch: 'selection {
    emit::loadImm(s.e, super::SCRATCH2, value);

    // When a case has block args, invert the branch to skip past
    // the arg moves.
    if args.len > 0 {
        let skip = s.nextSynthBlock;
        set s.nextSynthBlock = skip + 1;

        emit::recordBranch(s.e, skip, emit::BranchKind::InvertedCond {
            op: il::CmpOp::Eq, rs1, rs2: super::SCRATCH2,
        });
        emitBlockArgs(s, params, args);
        emit::recordBranch(s.e, target, emit::BranchKind::Jump);
        emit::recordBlock(s.e, skip);
    } else {
        emit::recordBranch(s.e, target, emit::BranchKind::Cond {
            op: il::CmpOp::Eq, rs1, rs2: super::SCRATCH2,
        });
    }
}

/// Move edge arguments and emit a jump unless its destination follows the block.
fn selectJump 'scratch 'selection (
    s: &mut Selector 'scratch 'selection,
    blockIdx: u32,
    target: u32,
    params: &[il::Param],
    args: &[il::Val]
) where 'scratch: 'selection {
    // Move arguments to target block's parameter registers.
    emitBlockArgs(s, params, args);
    // Skip branch if target is the next block (fallthrough).
    if target <> blockIdx + 1 {
        emit::recordBranch(s.e, target, emit::BranchKind::Jump);
    }
}

/// Select a conditional branch with parameters for its argument-bearing edge.
fn selectBranch 'input 'scratch 'selection (
    s: &mut Selector 'scratch 'selection,
    blockIdx: u32,
    instr: &il::published::Code 'input,
    params: &[il::Param],
    thenArgs: &[il::Val],
    elseArgs: &[il::Val]
) where 'scratch: 'selection {
    let case il::published::Code::Br { op, typ, a, b, thenTarget, elseTarget, .. } = *instr
        else panic "selectBranch: expected conditional branch";
    // Use zero register directly for immediate `0` operands.
    let aIsZero = isZeroImm(a);
    let bIsZero = isZeroImm(b);

    let rs1 = super::ZERO if aIsZero else resolveVal(s, super::SCRATCH1, a);
    let rs2 = super::ZERO if bIsZero else resolveVal(s, super::SCRATCH2, b);

    // Normalize sub-word operands so that both registers have the same
    // canonical representation. Without this, eg. `-1 : i8 ` loaded as
    // `0xFFFFFFFFFFFFFFFF` and `255 : i8` loaded as `0xFF` would compare
    // unequal even though they are the same 8-bit pattern.
    //
    // For SLT: sign-extension needed (signed comparison).
    // For ULT: zero-extension needed (unsigned magnitude comparison).
    // For EQ/NE with W32: sign-extension is cheaper.
    // For EQ/NE with W8/W16: keep zero-extension.
    // Skip extension for zero register.
    let mut signed = false;
    if let case il::CmpOp::Slt = op {
        set signed = true;
    }
    let useSext = cmpUsesSext(typ, signed);
    if not aIsZero and not isExtendedImm(a, typ, useSext) {
        emitCmpExt(s.e, rs1, rs1, typ, useSext);
    }
    if not bIsZero and not isExtendedImm(b, typ, useSext) {
        emitCmpExt(s.e, rs2, rs2, typ, useSext);
    }
    // Block-argument moves must only execute on the taken path.
    // When `thenArgs` is non-empty, invert the branch so that the
    // then-moves land on the fall-through (taken) side.
    //
    // When one target is the next block in layout order, we can
    // eliminate the trailing unconditional jump by arranging the
    // conditional branch to skip to the *other* target and letting
    // execution fall through.
    if thenArgs.len > 0 and elseArgs.len > 0 {
        panic "selectBranch: both `then` and `else` have block arguments";
    } else if thenArgs.len > 0 {
        emit::recordBranch(s.e, elseTarget, emit::BranchKind::InvertedCond { op, rs1, rs2 });
        // Skip trailing jump if then is the next block (fallthrough).
        selectJump(s, blockIdx, thenTarget, params, thenArgs);
    } else if thenTarget == blockIdx + 1 and elseArgs.len == 0 {
        // Then is the next block and no else args: invert the
        // condition to branch to else and fall through to then.
        emit::recordBranch(s.e, elseTarget, emit::BranchKind::InvertedCond { op, rs1, rs2 });
    } else {
        emit::recordBranch(s.e, thenTarget, emit::BranchKind::Cond { op, rs1, rs2 });
        // Skip trailing jump if else is the next block (fallthrough).
        selectJump(s, blockIdx, elseTarget, params, elseArgs);
    }
}

/// Select a call from its target, borrowed arguments, and optional result.
fn selectCall 'scratch 'selection (
    s: &mut Selector 'scratch 'selection,
    func: &il::Val,
    args: &[il::Val],
    dst: ?il::Reg
) where 'scratch: 'selection {
    // For indirect calls, save target to scratch register before arg
    // setup can clobber it.
    if let case il::Val::Reg(r) = *func {
        let target = getSrcReg(s, r, super::SCRATCH2);
        emitMv(s, super::SCRATCH2, target);
    }
    // Move arguments to A0-A7 using parallel move resolution.
    if args.len > super::ARG_REGS.len {
        set s.e.error = super::Error::Capacity;
        return;
    }
    emitParallelMoves(s, &super::ARG_REGS[..], args);

    // Emit call.
    match *func {
        case il::Val::FnAddr(name) => {
            emit::recordCall(s.e, name);
        },
        case il::Val::Reg(_) => {
            emit::emit(s.e, encode::jalr(super::RA, super::SCRATCH2, 0));
        },
        else => {
            panic "selectCall: invalid call target";
        }
    }
    // Move result from A0.
    if let d = dst {
        let rd = getDstReg(s, d, super::SCRATCH1);
        emitMv(s, rd, super::A0);
    }
}

/// Select RV64 instructions for inline IL operands.
fn selectFixedInstr 'scratch 'selection (s: &mut Selector 'scratch 'selection, blockIdx: u32, instr: &il::Instr, frame: &emit::Frame) where 'scratch: 'selection {
    match *instr {
        case il::Instr::BinOp { op, typ, dst, a, b } => {
            let rd = getDstReg(s, dst, super::SCRATCH1);
            let rs1 = resolveVal(s, super::SCRATCH1, a);
            selectAluBinOp(s, op, typ, rd, rs1, b);
        },
        case il::Instr::UnOp { op, typ, dst, a } => {
            let rd = getDstReg(s, dst, super::SCRATCH1);
            let rs = resolveVal(s, super::SCRATCH1, a);
            selectAluUnOp(s, op, typ, rd, rs);
        },
        case il::Instr::Load { typ, dst, src, offset } => {
            let rd = getDstReg(s, dst, super::SCRATCH1);
            let base = getSrcReg(s, src, super::SCRATCH2);
            emit::emitLoad(s.e, rd, base, offset, typ);
        },
        case il::Instr::Sload { typ, dst, src, offset } => {
            let rd = getDstReg(s, dst, super::SCRATCH1);
            let base = getSrcReg(s, src, super::SCRATCH2);
            emit::emitSload(s.e, rd, base, offset, typ);
        },
        case il::Instr::Store { typ, src, dst, offset } => {
            let base = getSrcReg(s, dst, super::SCRATCH2);
            let rs = resolveVal(s, super::SCRATCH1, src);
            emit::emitStore(s.e, rs, base, offset, typ);
        },
        case il::Instr::Copy { dst, val } => {
            let rd = getDstReg(s, dst, super::SCRATCH1);
            let rs = resolveVal(s, super::SCRATCH1, val);
            emitMv(s, rd, rs);
        },
        case il::Instr::Reserve { dst, size, alignment } => {
            match size {
                case il::Val::Imm(sz) => {
                    // Constant-sized reserve: use pre-allocated frame slot.
                    let rd = getDstReg(s, dst, super::SCRATCH1);
                    let aligned: i32 = mem::alignUpI32(s.reserveOffset, alignment as i32);
                    let base = spillBase(s);
                    let offset = s.ralloc.spill.frameSize + aligned
                        - (s.frameSize if s.isDynamic else 0);

                    emit::emitAddImm(s.e, rd, base, offset);
                    set s.reserveOffset = aligned + (sz as i32);
                },
                case il::Val::Reg(r) => {
                    // Dynamic-sized reserve: runtime SP adjustment.
                    let rd = getDstReg(s, dst, super::SCRATCH1);
                    let rs = getSrcReg(s, r, super::SCRATCH2);

                    emit::emit(s.e, encode::sub(super::SP, super::SP, rs));

                    if alignment > 1 {
                        let mask = 0 - alignment as i32;
                        assert encode::isSmallImm(mask);

                        emit::emit(s.e, encode::andi(super::SP, super::SP, mask));
                    }
                    emit::emit(s.e, encode::mv(rd, super::SP));
                },
                else =>
                    panic "selectFixedInstr: invalid reserve operand",
            }
        },
        case il::Instr::Blit { dst, src, size } => {
            let case il::Val::Imm(staticSize) = size else {
                set s.e.error = super::Error::Capacity; return;
            };
            if staticSize < 0 or staticSize > 0x7fffffff {
                set s.e.error = super::Error::Capacity; return;
            }
            if staticSize == 0 {
                return;
            }
            let rdst = getSrcReg(s, dst, super::SCRATCH2);
            let rsrc = getSrcReg(s, src, super::SCRATCH1);
            // Blit addresses have byte alignment. Small copies need no loop state.
            if staticSize < super::BLIT_LOOP_THRESHOLD as i64 {
                for offset in 0..staticSize as u32 {
                    emit::emitLb(s.e, super::ADDR_SCRATCH, rsrc, offset as i32);
                    emit::emitSb(s.e, super::ADDR_SCRATCH, rdst, offset as i32);
                }
            } else {
                // Private cursors preserve both input pointers. Save the count
                // register because it can hold a live allocated value.
                emit::emit(s.e, encode::addi(super::ADDR_SCRATCH, rsrc, 0));
                emit::emit(s.e, encode::addi(super::SCRATCH2, rdst, 0));
                emit::emit(s.e, encode::addi(super::SP, super::SP, -16));
                emit::emitSd(s.e, super::T3, super::SP, 0);
                emit::loadImm(s.e, super::T3, staticSize);
                let start = s.e.codeLen;
                emit::emitLb(s.e, super::SCRATCH1, super::ADDR_SCRATCH, 0);
                emit::emitSb(s.e, super::SCRATCH1, super::SCRATCH2, 0);
                emit::emit(s.e, encode::addi(super::ADDR_SCRATCH, super::ADDR_SCRATCH, 1));
                emit::emit(s.e, encode::addi(super::SCRATCH2, super::SCRATCH2, 1));
                emit::emit(s.e, encode::addi(super::T3, super::T3, -1));
                let offset = (start as i32 - s.e.codeLen as i32) * super::INSTR_SIZE;
                emit::emit(s.e, encode::bne(super::T3, super::ZERO, offset));
                emit::emitLd(s.e, super::T3, super::SP, 0);
                emit::emit(s.e, encode::addi(super::SP, super::SP, 16));
            }
        },
        case il::Instr::Zext { typ, dst, val } => {
            let rd = getDstReg(s, dst, super::SCRATCH1);
            let rs = resolveVal(s, super::SCRATCH1, val);
            emitZext(s.e, rd, rs, typ);
        },
        case il::Instr::Sext { typ, dst, val } => {
            let rd = getDstReg(s, dst, super::SCRATCH1);
            let rs = resolveVal(s, super::SCRATCH1, val);
            emitSext(s.e, rd, rs, typ);
        },
        case il::Instr::Ret { val } => {
            if let v = val {
                let rs = resolveVal(s, super::SCRATCH1, v);
                emitMv(s, super::A0, rs);
            }
            // Skip the jump to epilogue if this RET is in the last block,
            // since the epilogue immediately follows.
            if frame.totalSize <> 0 and blockIdx + 1 == frame.epilogueBlock {
                // Epilogue is the next block; fallthrough is sufficient.
            } else {
                emit::emitReturn(s.e, frame);
            }
        },
        case il::Instr::Unreachable => {
            emit::emit(s.e, encode::ebreak());
        },
        case il::Instr::Ecall { dst, num, a0, a1, a2, a3 } => {
            // Move arguments using parallel move.
            // TODO: Can't use slice literals here because the lowerer doesn't
            // support constant-evaluating struct/union values in them.
            let ecallDsts: [gen::Reg; 5] = [super::A7, super::A0, super::A1, super::A2, super::A3];
            let ecallArgs: [il::Val; 5] = [num, a0, a1, a2, a3];

            emitParallelMoves(s, &ecallDsts[..], &ecallArgs[..]);
            emit::emit(s.e, encode::ecall());

            // Result in A0.
            let ecallRd = getDstReg(s, dst, super::SCRATCH1);
            emitMv(s, ecallRd, super::A0);
        },
        case il::Instr::DeviceRead { typ, dst, handle, offset } => {
            deviceAddress(s, typ, handle, offset, il::Val::Imm(0), false);
            let rd = getDstReg(s, dst, super::SCRATCH1);
            match typ {
                case il::Type::W8 => emit::emit(s.e, encode::lbu(rd, super::A0, 0)),
                case il::Type::W16 => emit::emit(s.e, encode::lhu(rd, super::A0, 0)),
                case il::Type::W32 => emit::emit(s.e, encode::lwu(rd, super::A0, 0)),
                case il::Type::W64 => emit::emit(s.e, encode::ld(rd, super::A0, 0)),
            }
            emit::emit(s.e, encode::fence());
        },
        case il::Instr::DeviceWrite { typ, handle, offset, value } => {
            deviceAddress(s, typ, handle, offset, value, true);
            match typ {
                case il::Type::W8 => emit::emit(s.e, encode::sb(super::A3, super::A0, 0)),
                case il::Type::W16 => emit::emit(s.e, encode::sh(super::A3, super::A0, 0)),
                case il::Type::W32 => emit::emit(s.e, encode::sw(super::A3, super::A0, 0)),
                case il::Type::W64 => emit::emit(s.e, encode::sd(super::A3, super::A0, 0)),
            }
            emit::emit(s.e, encode::fence());
        },
        case il::Instr::Ebreak => {
            emit::emit(s.e, encode::ebreak());
        },
        case il::Instr::MemoryFence => {
            emit::emit(s.e, encode::fence());
        },
        case il::Instr::Call { .. }, il::Instr::Jmp { .. },
             il::Instr::Br { .. }, il::Instr::Switch { .. } =>
            panic "selectFixedInstr: expected inline operands",
    }
}

/// Choose the cheapest canonical representation that preserves the comparison.
/// RV64 word operations naturally sign-extend, and sign-extension preserves
/// unsigned ordering when both operands have the same declared width.
fn cmpUsesSext(typ: il::Type, signed: bool) -> bool {
    return signed or typ == il::Type::W32;
}

/// Extend a comparison operand to its selected canonical representation.
fn emitCmpExt(
    e: &mut emit::Emitter,
    rd: gen::Reg,
    rs: gen::Reg,
    typ: il::Type,
    useSext: bool
) {
    if useSext {
        emitSext(e, rd, rs, typ);
    } else {
        emitZext(e, rd, rs, typ);
    }
}

/// Truncate and extend an immediate exactly as its register operand would be.
fn canonicalCmpImm(imm: i64, typ: il::Type, useSext: bool) -> i64 {
    if useSext {
        match typ {
            case il::Type::W8 => return (imm as i8) as i64,
            case il::Type::W16 => return (imm as i16) as i64,
            case il::Type::W32 => return (imm as i32) as i64,
            case il::Type::W64 => return imm,
        }
    } else {
        match typ {
            case il::Type::W8 => return (imm as u8) as i64,
            case il::Type::W16 => return (imm as u16) as i64,
            case il::Type::W32 => return (imm as u32) as i64,
            case il::Type::W64 => return imm,
        }
    }
}

/// Check if a value is an immediate that's already correctly extended.
/// `loadImm` produces the exact 64-bit value; this checks whether that value
/// already matches what sign/zero-extension to the given type would produce.
fn isExtendedImm(val: il::Val, typ: il::Type, signed: bool) -> bool {
    if let case il::Val::Imm(imm) = val {
        if signed {
            // Sign-extension truncates to the type width and sign-extends.
            // The 64-bit value is already correctly sign-extended if it
            // fits in the signed range of the target type.
            match typ {
                case il::Type::W8 => return imm >= I8_MIN and imm <= I8_MAX,
                case il::Type::W16 => return imm >= I16_MIN and imm <= I16_MAX,
                case il::Type::W32 => return imm >= I32_MIN and imm <= I32_MAX,
                case il::Type::W64 => return true,
            }
        } else {
            // Zero-extension: value must be non-negative and within unsigned range.
            match typ {
                case il::Type::W8 => return imm >= 0 and imm <= U8_MAX,
                case il::Type::W16 => return imm >= 0 and imm <= U16_MAX,
                case il::Type::W32 => return imm >= 0 and imm <= U32_MAX,
                case il::Type::W64 => return true,
            }
        }
    }
    return false;
}

/// Check if a value is an immediate zero.
fn isZeroImm(val: il::Val) -> bool {
    if let case il::Val::Imm(imm) = val {
        return imm == 0;
    }
    return false;
}

/// Select a binary ALU operation, dispatching to the appropriate
/// instruction pattern based on the operation kind and type.
fn selectAluBinOp 'scratch 'selection (s: &mut Selector 'scratch 'selection, op: il::BinOp, typ: il::Type, rd: gen::Reg, rs1: gen::Reg, b: il::Val) where 'scratch: 'selection {
    match op {
        case il::BinOp::Add => {
            if typ == il::Type::W32 {
                // Inline W32 ADD with immediate optimization.
                if let case il::Val::Imm(imm) = b {
                    if encode::isSmallImm64(imm) {
                        emit::emit(s.e, encode::addiw(rd, rs1, imm as i32));
                        return;
                    }
                }
                let rs2 = resolveVal(s, super::SCRATCH2, b);
                emit::emit(s.e, encode::addw(rd, rs1, rs2));
            } else {
                selectBinOp(s, rd, rs1, b, BinOp::Add, super::SCRATCH2);
            }
        }
        case il::BinOp::Sub => {
            // Optimize subtraction by small immediate: use ADDI with negated value.
            if let case il::Val::Imm(imm) = b {
                let neg = -imm;
                if neg >= super::MIN_IMM as i64 and neg <= super::MAX_IMM as i64 {
                    emit::emit(s.e,
                        encode::addiw(rd, rs1, neg as i32)
                            if typ == il::Type::W32 else
                        encode::addi(rd, rs1, neg as i32));
                    return;
                }
            }
            let rs2 = resolveVal(s, super::SCRATCH2, b);

            emit::emit(s.e,
                encode::subw(rd, rs1, rs2)
                    if typ == il::Type::W32 else
                encode::sub(rd, rs1, rs2));
        }
        case il::BinOp::Mul => {
            // Strength-reduce multiplication by known constants.
            if let case il::Val::Imm(imm) = b {
                if imm == 0 {
                    emit::emit(s.e, encode::mv(rd, super::ZERO));
                    return;
                } else if imm == 1 {
                    emitMv(s, rd, rs1);
                    return;
                } else if imm == 2 {
                    emit::emit(s.e, encode::slli(rd, rs1, 1));
                    return;
                } else if imm == 4 {
                    emit::emit(s.e, encode::slli(rd, rs1, 2));
                    return;
                } else if imm == 8 {
                    emit::emit(s.e, encode::slli(rd, rs1, 3));
                    return;
                }
            }
            let rs2 = resolveVal(s, super::SCRATCH2, b);
            emit::emit(s.e,
                encode::mulw(rd, rs1, rs2)
                    if typ == il::Type::W32 else
                encode::mul(rd, rs1, rs2));
        }
        case il::BinOp::Sdiv => {
            let rs2 = resolveAndTrapIfZero(s, b, typ, true);
            emit::emit(s.e,
                encode::divw(rd, rs1, rs2)
                    if typ == il::Type::W32 else
                encode::div(rd, rs1, rs2));
        }
        case il::BinOp::Udiv => {
            let rs2 = resolveAndTrapIfZero(s, b, typ, false);
            emit::emit(s.e,
                encode::divuw(rd, rs1, rs2)
                    if typ == il::Type::W32 else
                encode::divu(rd, rs1, rs2));
        }
        case il::BinOp::Srem => {
            let rs2 = resolveAndTrapIfZero(s, b, typ, true);
            emit::emit(s.e,
                encode::remw(rd, rs1, rs2)
                    if typ == il::Type::W32 else
                encode::rem(rd, rs1, rs2));
        }
        case il::BinOp::Urem => {
            let rs2 = resolveAndTrapIfZero(s, b, typ, false);
            emit::emit(s.e,
                encode::remuw(rd, rs1, rs2)
                    if typ == il::Type::W32 else
                encode::remu(rd, rs1, rs2));
        }
        case il::BinOp::And =>
            selectBinOp(s, rd, rs1, b, BinOp::And, super::SCRATCH2),
        case il::BinOp::Or =>
            selectBinOp(s, rd, rs1, b, BinOp::Or, super::SCRATCH2),
        case il::BinOp::Xor =>
            selectBinOp(s, rd, rs1, b, BinOp::Xor, super::SCRATCH2),
        case il::BinOp::Shl =>
            selectShift(s, rd, rs1, b, ShiftOp::Sll, typ, super::SCRATCH2),
        case il::BinOp::Sshr =>
            selectShift(s, rd, rs1, b, ShiftOp::Sra, typ, super::SCRATCH2),
        case il::BinOp::Ushr =>
            selectShift(s, rd, rs1, b, ShiftOp::Srl, typ, super::SCRATCH2),
        case il::BinOp::Eq, il::BinOp::Ne => {
            let rs2 = resolveVal(s, super::SCRATCH2, b);
            let useSext = cmpUsesSext(typ, false);
            emitCmpExt(s.e, rs1, rs1, typ, useSext);
            if not isExtendedImm(b, typ, useSext) {
                emitCmpExt(s.e, rs2, rs2, typ, useSext);
            }
            emit::emit(s.e, encode::xor(rd, rs1, rs2));
            if let case il::BinOp::Eq = op {
                emit::emit(s.e, encode::sltiu(rd, rd, 1));
            } else {
                emit::emit(s.e, encode::sltu(rd, super::ZERO, rd));
            }
        }
        case il::BinOp::Slt =>
            selectCmp(s, typ, rd, rs1, b, CmpOp::Slt, false, super::SCRATCH2),
        case il::BinOp::Ult =>
            selectCmp(s, typ, rd, rs1, b, CmpOp::Ult, false, super::SCRATCH2),
        case il::BinOp::Sge =>
            selectCmp(s, typ, rd, rs1, b, CmpOp::Slt, true, super::SCRATCH2),
        case il::BinOp::Uge =>
            selectCmp(s, typ, rd, rs1, b, CmpOp::Ult, true, super::SCRATCH2),
    }
}

/// Select a unary ALU operation.
fn selectAluUnOp 'scratch 'selection (s: &mut Selector 'scratch 'selection, op: il::UnOp, typ: il::Type, rd: gen::Reg, rs: gen::Reg) where 'scratch: 'selection {
    match op {
        case il::UnOp::Neg => {
            if typ == il::Type::W32 {
                emit::emit(s.e, encode::subw(rd, super::ZERO, rs));
            } else {
                emit::emit(s.e, encode::neg(rd, rs));
            }
        }
        case il::UnOp::Not =>
            emit::emit(s.e, encode::not_(rd, rs)),
    }
}

/// Select binary operation with immediate optimization.
fn selectBinOp 'scratch 'selection (s: &mut Selector 'scratch 'selection, rd: gen::Reg, rs1: gen::Reg, b: il::Val, op: BinOp, scratch: gen::Reg) where 'scratch: 'selection {
    // Try immediate optimization first.
    if let case il::Val::Imm(imm) = b {
        if encode::isSmallImm64(imm) {
            let simm = imm as i32;
            match op {
                case BinOp::Add => emit::emit(s.e, encode::addi(rd, rs1, simm)),
                case BinOp::And => emit::emit(s.e, encode::andi(rd, rs1, simm)),
                case BinOp::Or  => emit::emit(s.e, encode::ori(rd, rs1, simm)),
                case BinOp::Xor => emit::emit(s.e, encode::xori(rd, rs1, simm)),
            }
            return;
        }
    }
    // Fallback: load into register.
    let rs2 = resolveVal(s, scratch, b);
    match op {
        case BinOp::Add => emit::emit(s.e, encode::add(rd, rs1, rs2)),
        case BinOp::And => emit::emit(s.e, encode::and_(rd, rs1, rs2)),
        case BinOp::Or  => emit::emit(s.e, encode::or_(rd, rs1, rs2)),
        case BinOp::Xor => emit::emit(s.e, encode::xor(rd, rs1, rs2)),
    }
}

/// Select shift operation with immediate optimization.
/// For 32-bit operations, uses the `*w` variants that operate on the lower 32 bits
/// and sign-extend the result.
fn selectShift 'scratch 'selection (s: &mut Selector 'scratch 'selection, rd: gen::Reg, rs1: gen::Reg, b: il::Val, op: ShiftOp, typ: il::Type, scratch: gen::Reg) where 'scratch: 'selection {
    let isW32: bool = typ == il::Type::W32;

    // Try immediate optimization first.
    if let case il::Val::Imm(shamt) = b {
        // Keep immediate forms only for encodable shift amounts.
        // Otherwise fall back to register shifts, which naturally mask the count.
        if shamt >= 0 and ((isW32 and shamt < 32) or (not isW32 and shamt < 64)) {
            let sa = shamt as i32;
            if isW32 {
                match op {
                    case ShiftOp::Sll => emit::emit(s.e, encode::slliw(rd, rs1, sa)),
                    case ShiftOp::Srl => emit::emit(s.e, encode::srliw(rd, rs1, sa)),
                    case ShiftOp::Sra => emit::emit(s.e, encode::sraiw(rd, rs1, sa)),
                }
            } else {
                match op {
                    case ShiftOp::Sll => emit::emit(s.e, encode::slli(rd, rs1, sa)),
                    case ShiftOp::Srl => emit::emit(s.e, encode::srli(rd, rs1, sa)),
                    case ShiftOp::Sra => emit::emit(s.e, encode::srai(rd, rs1, sa)),
                }
            }
            return;
        }
    }
    // Fallback: load into register.
    let rs2 = resolveVal(s, scratch, b);
    if isW32 {
        match op {
            case ShiftOp::Sll => emit::emit(s.e, encode::sllw(rd, rs1, rs2)),
            case ShiftOp::Srl => emit::emit(s.e, encode::srlw(rd, rs1, rs2)),
            case ShiftOp::Sra => emit::emit(s.e, encode::sraw(rd, rs1, rs2)),
        }
    } else {
        match op {
            case ShiftOp::Sll => emit::emit(s.e, encode::sll(rd, rs1, rs2)),
            case ShiftOp::Srl => emit::emit(s.e, encode::srl(rd, rs1, rs2)),
            case ShiftOp::Sra => emit::emit(s.e, encode::sra(rd, rs1, rs2)),
        }
    }
}

/// Resolve parallel moves from IL values to physical destination registers.
///
/// The parallel move problem arises when moving values between registers where
/// there may be dependencies (e.g. moving A0 to A1 and A1 to A0 simultaneously).
///
/// This algorithm:
/// 1. Identifies "ready" moves.
/// 2. Executes ready moves.
/// 3. Breaks cycles using scratch register.
///
/// Entries with `ZERO` destination are skipped, as they are handled by caller.
fn emitParallelMoves 'scratch 'selection (s: &mut Selector 'scratch 'selection, dsts: &[gen::Reg], args: &[il::Val]) where 'scratch: 'selection {
    let n: u32 = args.len;
    if n == 0 {
        return;
    }
    if n > MAX_BLOCK_ARGS {
        set s.e.error = super::Error::Capacity;
        return;
    }
    // Source registers for each arg.
    let mut srcRegs: [gen::Reg; MAX_BLOCK_ARGS] = [super::ZERO; MAX_BLOCK_ARGS];
    // If this is a register-to-register move.
    let mut isRegMove: [bool; MAX_BLOCK_ARGS] = [false; MAX_BLOCK_ARGS];
    // If this move still needs to be executed.
    let mut pending: [bool; MAX_BLOCK_ARGS] = [false; MAX_BLOCK_ARGS];
    // Number of pending moves.
    let mut numPending: u32 = 0;

    for i in 0..n {
        let dst = dsts[i];
        if dst <> super::ZERO { // Skip entries with no destination.
            match args[i] {
                case il::Val::Reg(r) => {
                    if let _ = regalloc::spill::spillSlot(&s.ralloc.spill, r) {
                        // Spilled value needs load, not a register move.
                        set pending[i] = true;
                        set numPending += 1;
                    } else {
                        let src = getReg(s, r);
                        if src <> dst {
                            // Register-to-register move needed.
                            set srcRegs[i] = src;
                            set isRegMove[i] = true;
                            set pending[i] = true;
                            set numPending += 1;
                        } else {
                            // No move needed.
                        }
                    }
                },
                case il::Val::Imm(_), il::Val::DataSym(_), il::Val::FnAddr(_) => {
                    set pending[i] = true;
                    set numPending += 1;
                },
                case il::Val::Undef => {
                    // Undefined values don't need any move.
                }
            }
        } else {
            // Nothing to do.
        }
    }

    // Execute parallel move algorithm.
    while numPending > 0 {
        let mut found = false;

        // Find a ready move: one whose destination is not a source of any
        // pending register move.
        for i in 0..n {
            if pending[i] {
                let dst = dsts[i];
                let mut isReady = true;

                // Check if `dst` is used as source by any other pending register move.
                for j in 0..n {
                    if j <> i and pending[j] and isRegMove[j] and srcRegs[j] == dst {
                        set isReady = false;
                        break;
                    }
                }
                if isReady {
                    // Execute this move.
                    if isRegMove[i] {
                        emitMv(s, dst, srcRegs[i]);
                    } else {
                        // Load immediate, symbol, or spilled value.
                        loadVal(s, dst, args[i]);
                    }
                    set found = true;
                    set pending[i] = false;
                    set numPending -= 1;

                    break;
                }
            }
        }

        if not found {
            // No ready move, we have a cycle among register moves.
            // Break it by saving one source to scratch.
            for i in 0..n {
                if pending[i] and isRegMove[i] {
                    let src = srcRegs[i];
                    // Save this source to scratch.
                    emitMv(s, super::SCRATCH1, src);
                    // Update all pending moves that use this source.
                    for j in 0..n {
                        if pending[j] and isRegMove[j] and srcRegs[j] == src {
                            set srcRegs[j] = super::SCRATCH1;
                        }
                    }
                    break;
                }
            }
        }
    }
}

/// Emit moves from block arguments to target block's parameter registers.
///
/// Handles spilled destinations directly, then delegates to [`emitParallelMoves`]
/// for the remaining register-to-register parallel move resolution. Edges that
/// would overwrite an unconsumed spill source are unsupported.
fn emitBlockArgs 'scratch 'selection (s: &mut Selector 'scratch 'selection, params: &[il::Param], args: &[il::Val]) where 'scratch: 'selection {
    if args.len == 0 {
        return;
    }
    assert args.len == params.len, "emitBlockArgs: argument/parameter count mismatch";
    if args.len > MAX_BLOCK_ARGS {
        set s.e.error = super::Error::Capacity;
        return;
    }

    // The parallel-move resolver only handles register destinations. Keep eager
    // stores for independent spill slots, but reject dependencies that would
    // require stack staging rather than silently miscompiling them.
    for arg, i in args {
        if let dstSlot = regalloc::spill::spillSlot(&s.ralloc.spill, params[i].value) {
            let mut changesSlot = true;
            if let case il::Val::Reg(src) = arg {
                if let srcSlot = regalloc::spill::spillSlot(&s.ralloc.spill, src) {
                    if srcSlot == dstSlot {
                        set changesSlot = false;
                    }
                }
            }
            if changesSlot {
                for source, j in args {
                    if let case il::Val::Reg(src) = source {
                        if let sourceSlot = regalloc::spill::spillSlot(&s.ralloc.spill, src) {
                            if sourceSlot == dstSlot {
                                if let sourceDstSlot = regalloc::spill::spillSlot(
                                    &s.ralloc.spill, params[j].value
                                ) {
                                    assert sourceDstSlot == dstSlot or j < i,
                                        "emitBlockArgs: overlapping spilled block arguments are unsupported";
                                } else {
                                    panic "emitBlockArgs: overlapping spilled block arguments are unsupported";
                                }
                            }
                        }
                    }
                }
            }
        }
    }

    // Destination registers for each arg.
    // Zero means the destination is spilled or skipped.
    let mut dsts: [gen::Reg; MAX_BLOCK_ARGS] = [super::ZERO; MAX_BLOCK_ARGS];

    for arg, i in args {
        let param = params[i].value;

        // Spilled destinations: store directly to spill slot.
        // These don't participate in the parallel move algorithm.
        if let slot = regalloc::spill::spillSlot(&s.ralloc.spill, param) {
            if let case il::Val::Undef = arg {
                // Undefined values don't need any move.
            } else {
                let rs = resolveVal(s, super::SCRATCH1, arg);
                emit::emitSd(s.e, rs, spillBase(s), spillOffset(s, slot));
            }
        } else {
            set dsts[i] = getReg(s, param);
        }
    }
    emitParallelMoves(s, &dsts[..], args);
}

/// Select a comparison with immediate optimization.
fn selectCmp 'scratch 'selection (
    s: &mut Selector 'scratch 'selection,
    typ: il::Type,
    rd: gen::Reg,
    rs1: gen::Reg,
    b: il::Val,
    op: CmpOp,
    invert: bool,
    scratch: gen::Reg
) where 'scratch: 'selection {
    let mut signed = false;
    if let case CmpOp::Slt = op {
        set signed = true;
    }
    let useSext = cmpUsesSext(typ, signed);
    emitCmpExt(s.e, rs1, rs1, typ, useSext);

    // Canonicalizing the immediate can expose an immediate instruction even
    // when the IL value used a different representation for the same width.
    let mut rhs = b;
    if let case il::Val::Imm(imm) = b {
        let canonical = canonicalCmpImm(imm, typ, useSext);
        set rhs = il::Val::Imm(canonical);
        if encode::isSmallImm64(canonical) {
            let simm = canonical as i32;
            match op {
                case CmpOp::Slt => emit::emit(s.e, encode::slti(rd, rs1, simm)),
                case CmpOp::Ult => emit::emit(s.e, encode::sltiu(rd, rs1, simm)),
            }
            if invert {
                emit::emit(s.e, encode::xori(rd, rd, 1));
            }
            return;
        }
    }

    let rs2 = resolveVal(s, scratch, rhs);
    if not isExtendedImm(rhs, typ, useSext) {
        emitCmpExt(s.e, rs2, rs2, typ, useSext);
    }
    match op {
        case CmpOp::Slt => emit::emit(s.e, encode::slt(rd, rs1, rs2)),
        case CmpOp::Ult => emit::emit(s.e, encode::sltu(rd, rs1, rs2)),
    }
    if invert {
        emit::emit(s.e, encode::xori(rd, rd, 1));
    }
}

/// Resolve one live Device access before an ordered user-mode register instruction.
fn deviceAddress 'scratch 'selection (
    s: &mut Selector 'scratch 'selection,
    typ: il::Type,
    handle: il::Val,
    offset: il::Val,
    value: il::Val,
    writing: bool
) where 'scratch: 'selection {
    let mut flags = il::typeSize(typ) as i64;
    if writing {
        set flags |= 0x100;
    }
    let dsts: [gen::Reg; 5] = [super::A7, super::A0, super::A1, super::A2, super::A3];
    let args: [il::Val; 5] = [il::Val::Imm(il::DEVICE_ACCESS as i64), handle, offset, il::Val::Imm(flags), value];
    emitParallelMoves(s, &dsts[..], &args[..]);
    emit::emit(s.e, encode::ecall());
    emit::emit(s.e, encode::fence());
}