//! RV64 atomic instruction fields and canonical assembly names.

use std::mem;

use std::lang::gen;

/// Atomic operation, width, and ordering fields.

export record Format: Copy {

    /// Five-bit operation code from the A extension.

    operation: u32,

    /// Memory width encoding: 2 for a word, 3 for a doubleword.

    width: u32,

    /// Ordering bits: 2 for acquire, 1 for release, 3 for both.

    order: u32,

}

/// Decoded atomic instruction operands.

export record Instruction: Copy {

    /// Operation and ordering fields.

    format: Format,

    /// Destination register.

    rd: gen::Reg,

    /// Address register.

    rs1: gen::Reg,

    /// Source value; zero for load-reserved.

    rs2: gen::Reg,

}

/// An architectural operation and its mnemonic stem.

record Operation: Copy {

    /// Mnemonic without width or ordering suffixes.

    name: *[u8],

    /// Five-bit instruction field.

    code: u32,

}

/// Operations shared by the 32-bit and 64-bit forms.

constant OPERATIONS: [Operation; 11] = [

    { name: "amoadd", code: 0 }, { name: "amoswap", code: 1 },

    { name: "lr", code: 2 }, { name: "sc", code: 3 },

    { name: "amoxor", code: 4 }, { name: "amoor", code: 8 },

    { name: "amoand", code: 12 }, { name: "amomin", code: 16 },

    { name: "amomax", code: 20 }, { name: "amominu", code: 24 },

    { name: "amomaxu", code: 28 },

];

/// Look up an operation's canonical mnemonic stem.

export fn name(code: u32) -> ?*[u8] {

    for operation in &OPERATIONS[..] {

        if operation.code == code {

            return operation.name;

        }

    }

    return nil;

}

/// Parse an atomic mnemonic with mandatory width and optional ordering suffix.

export fn parse(text: *[u8]) -> ?Format {

    for operation in &OPERATIONS[..] {

        let n = operation.name.len;

        if text.len < n + 2 or not mem::eq(&text[..n], operation.name) or text[n] <> '.' {

            continue;

        }

        let mut width: u32 = 2;

        if text[n + 1] == 'd' {

            set width = 3;

        }

        else if text[n + 1] <> 'w' {

            return nil;

        }

        let suffix = &text[n + 2..];

        let mut order: u32 = 0;

        if mem::eq(suffix, ".aq") {

            set order = 2;

        }

        else if mem::eq(suffix, ".rl") {

            set order = 1;

        }

        else if mem::eq(suffix, ".aqrl") {

            set order = 3;

        }

        else if suffix.len <> 0 {

            return nil;

        }

        return Format { operation: operation.code, width, order };

    }

    return nil;

}

/// Encode a validated atomic operation and register operands.

export fn encode(instruction: Instruction) -> u32 {

    let format = instruction.format;

    assert name(format.operation) <> nil and (format.width == 2 or format.width == 3) and format.order <= 3;

    assert format.operation <> 2 or instruction.rs2 == super::ZERO;

    return 0x2f | (*instruction.rd as u32 << 7) | (format.width << 12)

        | (*instruction.rs1 as u32 << 15) | (*instruction.rs2 as u32 << 20)

        | (format.order << 25) | (format.operation << 27);

}

/// Decode a supported atomic word and reject reserved width and LR fields.

export fn decode(word: u32) -> ?Instruction {

    let operation = word >> 27;

    let width = (word >> 12) & 7;

    let rs2 = super::reg(((word >> 20) & 31) as u8);

    if (word & 127) <> 0x2f or name(operation) == nil or (width <> 2 and width <> 3) {

        return nil;

    }

    if operation == 2 and rs2 <> super::ZERO {

        return nil;

    }

    return Instruction {

        format: Format { operation, width, order: (word >> 25) & 3 },

        rd: super::reg(((word >> 7) & 31) as u8), rs1: super::reg(((word >> 15) & 31) as u8), rs2,

    };

}