riscv/
debug.c
21.3 KiB
debug.h
1.8 KiB
.clang-format
570 B
.gitignore
5 B
.gitsigners
112 B
LICENSE
1.1 KiB
Makefile
1.1 KiB
README
3.3 KiB
color.h
567 B
emulator.c
79.7 KiB
io.c
1.1 KiB
io.h
444 B
jit.c
32.6 KiB
jit.h
5.0 KiB
riscv.c
12.0 KiB
riscv.h
12.0 KiB
types.h
1.0 KiB
riscv/debug.h
raw
| 1 | #ifndef OP_DEBUG_H |
| 2 | #define OP_DEBUG_H |
| 3 | |
| 4 | #include <stdio.h> |
| 5 | |
| 6 | #include "../riscv.h" |
| 7 | #include "../types.h" |
| 8 | |
| 9 | /* Maximum length of a component string (op, reg, imm). */ |
| 10 | #define MAX_PART_LEN 16 |
| 11 | /* Maximum length of an instruction string, including colors. */ |
| 12 | #define MAX_INSTR_STR_LEN 96 |
| 13 | /* Length of an instruction string, without colors. */ |
| 14 | #define INSTR_STR_LEN 24 |
| 15 | |
| 16 | /* Structure for representing a decoded RISC-V instruction's components. |
| 17 | * All components are stored as strings to allow for syntax highlighting. */ |
| 18 | struct instrparts { |
| 19 | /* Operation name (e.g., "add", "lw", "beq") */ |
| 20 | char op[MAX_PART_LEN]; |
| 21 | /* Destination register (e.g., "a0", "t0") */ |
| 22 | char rd[MAX_PART_LEN]; |
| 23 | /* Source register 1 (e.g., "a1", "t1") */ |
| 24 | char rs1[MAX_PART_LEN]; |
| 25 | /* Source register 2 (e.g., "a2", "t2") */ |
| 26 | char rs2[MAX_PART_LEN]; |
| 27 | /* Immediate value as string (e.g., "42", "-8") */ |
| 28 | char imm[MAX_PART_LEN]; |
| 29 | /* Memory offset (e.g., "8" in "lw t0, 8(sp)") */ |
| 30 | char off[MAX_PART_LEN]; |
| 31 | /* For memory operations, base register (e.g., "sp" in "lw t0, 8(sp)") */ |
| 32 | char base[MAX_PART_LEN]; |
| 33 | /* Type of the instruction (R, I, S, B, U, J) */ |
| 34 | char type; |
| 35 | /* Whether the instruction is a pseudo-instruction (e.g., mv, li, ret) */ |
| 36 | bool is_pseudo; |
| 37 | }; |
| 38 | |
| 39 | /** |
| 40 | * Convert an instruction to a human-readable RISC-V assembly string. |
| 41 | */ |
| 42 | i32 sprint_instr(instr_t instr, char *str, bool color); |
| 43 | |
| 44 | /** |
| 45 | * Prints a human-readable RISC-V assembly representation of the instruction to |
| 46 | * the given stream. |
| 47 | */ |
| 48 | void print_instr( |
| 49 | instr_t instr, FILE *stream, const char *comment, bool color, i32 indent |
| 50 | ); |
| 51 | |
| 52 | /** |
| 53 | * Prints human-readable RISC-V assembly representations of multiple |
| 54 | * instructions to the given stream. |
| 55 | */ |
| 56 | void print_instrs( |
| 57 | instr_t *instrs, usize count, FILE *stream, const char *comment |
| 58 | ); |
| 59 | |
| 60 | #endif /* OP_DEBUG_H */ |