radiance · Radiance self-hosting compiler

compiler/ lib/ examples/ std/ arch/ rv64/ tests/ decode.rad 14.6 KiB emit.rad 24.4 KiB encode.rad 19.9 KiB isel.rad 41.1 KiB printer.rad 13.0 KiB tests.rad 15.7 KiB rv64.rad 13.0 KiB collections/ lang/ sys/ arch.rad 65 B collections.rad 36 B fmt.rad 3.8 KiB intrinsics.rad 206 B io.rad 1.2 KiB lang.rad 222 B mem.rad 2.2 KiB sys.rad 167 B testing.rad 2.4 KiB tests.rad 11.6 KiB vec.rad 3.1 KiB std.rad 231 B scripts/ seed/ test/ vim/ .gitignore 353 B .gitsigners 112 B LICENSE 1.1 KiB Makefile 3.1 KiB README 2.5 KiB std.lib 987 B std.lib.test 252 B
lib/std/arch/rv64/encode.rad 19.9 KiB raw
//! RISC-V RV64I+M instruction encoding.
//!
//! Provides type-safe functions for encoding RV64 instructions.

//////////////////////
// Opcode Constants //
//////////////////////

pub const OP_LOAD:   u32 = 0x03;
pub const OP_STORE:  u32 = 0x23;
pub const OP_BRANCH: u32 = 0x63;
pub const OP_JALR:   u32 = 0x67;
pub const OP_JAL:    u32 = 0x6F;
pub const OP_OP:     u32 = 0x33;
pub const OP_IMM:    u32 = 0x13;
pub const OP_AUIPC:  u32 = 0x17;
pub const OP_LUI:    u32 = 0x37;
pub const OP_SYSTEM: u32 = 0x73;
pub const OP_OP32:   u32 = 0x3B;  // RV64: 32-bit operations
pub const OP_IMM32:  u32 = 0x1B;  // RV64: 32-bit immediate operations

//////////////////////
// Funct3 Constants //
//////////////////////

// Memory operations

pub const F3_BYTE:   u32 = 0x0;  // LB/SB
pub const F3_HALF:   u32 = 0x1;  // LH/SH
pub const F3_WORD:   u32 = 0x2;  // LW/SW
pub const F3_DWORD:  u32 = 0x3;  // LD/SD (RV64)
pub const F3_BYTE_U: u32 = 0x4;  // LBU
pub const F3_HALF_U: u32 = 0x5;  // LHU
pub const F3_WORD_U: u32 = 0x6;  // LWU (RV64)

// ALU operations

pub const F3_ADD:  u32 = 0x0;  // ADD/SUB/ADDI
pub const F3_SLL:  u32 = 0x1;  // SLL/SLLI
pub const F3_SLT:  u32 = 0x2;  // SLT/SLTI
pub const F3_SLTU: u32 = 0x3;  // SLTU/SLTIU
pub const F3_XOR:  u32 = 0x4;  // XOR/XORI
pub const F3_SRL:  u32 = 0x5;  // SRL/SRA/SRLI/SRAI
pub const F3_OR:   u32 = 0x6;  // OR/ORI
pub const F3_AND:  u32 = 0x7;  // AND/ANDI

// Branch operations

pub const F3_BEQ:  u32 = 0x0;
pub const F3_BNE:  u32 = 0x1;
pub const F3_BLT:  u32 = 0x4;
pub const F3_BGE:  u32 = 0x5;
pub const F3_BLTU: u32 = 0x6;
pub const F3_BGEU: u32 = 0x7;

//////////////////////
// Funct7 Constants //
//////////////////////

pub const F7_NORMAL: u32 = 0b0000000;
pub const F7_SUB:    u32 = 0b0100000;  // Bit 5 set
pub const F7_SRA:    u32 = 0b0100000;  // Bit 5 set
pub const F7_MUL:    u32 = 0b0000001;  // Bit 0 set

/////////////////////////
// Validation Helpers  //
/////////////////////////

/// Returns `true` if the value fits in a signed 12-bit immediate.
pub fn isSmallImm(value: i32) -> bool {
    return value >= super::MIN_IMM and value <= super::MAX_IMM;
}

/// Returns `true` if a 64-bit value fits in a 12-bit signed immediate.
pub fn isSmallImm64(value: i64) -> bool {
    return value >= (super::MIN_IMM as i64) and value <= (super::MAX_IMM as i64);
}

/// Returns `true` if the value is valid for branch immediates.
/// Branch immediates are 13-bit signed, even aligned.
pub fn isBranchImm(value: i32) -> bool {
    return value >= -(1 << 12) and value <= ((1 << 12) - 2) and (value & 1) == 0;
}

/// Returns `true` if the value is valid for jump immediates (JAL).
/// Jump immediates are 21-bit signed, even aligned.
pub fn isJumpImm(value: i32) -> bool {
    return value >= -(1 << 20) and value <= ((1 << 20) - 2) and (value & 1) == 0;
}

//////////////////////
// Format Encoders  //
//////////////////////

/// Encode an R-type instruction.
fn encodeR(opcode: u32, rd: super::Reg, rs1: super::Reg, rs2: super::Reg, funct3: u32, funct7: u32) -> u32 {
    return (opcode        & 0x7F)
         | ((rd.n  as u32 & 0x1F) << 7)
         | ((funct3       & 0x07) << 12)
         | ((rs1.n as u32 & 0x1F) << 15)
         | ((rs2.n as u32 & 0x1F) << 20)
         | ((funct7       & 0x7F) << 25);
}

/// Encode an I-type instruction.
fn encodeI(opcode: u32, rd: super::Reg, rs1: super::Reg, funct3: u32, imm: i32) -> u32 {
    assert isSmallImm(imm);

    return (opcode        & 0x7F)
         | ((rd.n  as u32 & 0x1F)  << 7)
         | ((funct3       & 0x07)  << 12)
         | ((rs1.n as u32 & 0x1F)  << 15)
         | ((imm as u32   & 0xFFF) << 20);
}

/// Encode an S-type instruction.
fn encodeS(opcode: u32, rs1: super::Reg, rs2: super::Reg, funct3: u32, imm: i32) -> u32 {
    assert isSmallImm(imm);

    return (opcode  & 0x7F)
         | ((imm as u32        & 0x1F) << 7)
         | ((funct3            & 0x07) << 12)
         | ((rs1.n as u32      & 0x1F) << 15)
         | ((rs2.n as u32      & 0x1F) << 20)
         | ((imm as u32 >> 5   & 0x7F) << 25);
}

/// Encode a B-type (branch) instruction.
fn encodeB(opcode: u32, rs1: super::Reg, rs2: super::Reg, funct3: u32, imm: i32) -> u32 {
    assert isBranchImm(imm);

    let imm11   = (imm as u32 >> 11) & 0x1;
    let imm4_1  = (imm as u32 >> 1)  & 0xF;
    let imm10_5 = (imm as u32 >> 5)  & 0x3F;
    let imm12   = (imm as u32 >> 12) & 0x1;

    return (opcode        &  0x7F)
         | (imm11         << 7)
         | (imm4_1        << 8)
         | ((funct3       & 0x07) << 12)
         | ((rs1.n as u32 & 0x1F) << 15)
         | ((rs2.n as u32 & 0x1F) << 20)
         | (imm10_5       << 25)
         | (imm12         << 31);
}

/// Encode a U-type instruction.
fn encodeU(opcode: u32, rd: super::Reg, imm: i32) -> u32 {
    return (opcode       & 0x7F)
         | ((rd.n as u32 & 0x1F)    << 7)
         | ((imm as u32  & 0xFFFFF) << 12);
}

/// Encode a J-type (jump) instruction.
fn encodeJ(opcode: u32, rd: super::Reg, imm: i32) -> u32 {
    assert isJumpImm(imm);

    let imm20    = (imm as u32 >> 20) & 0x1;
    let imm10_1  = (imm as u32 >> 1)  & 0x3FF;
    let imm11    = (imm as u32 >> 11) & 0x1;
    let imm19_12 = (imm as u32 >> 12) & 0xFF;

    return (opcode       & 0x7F)
         | ((rd.n as u32 & 0x1F) << 7)
         | (imm19_12     << 12)
         | (imm11        << 20)
         | (imm10_1      << 21)
         | (imm20        << 31);
}

////////////////////////////
// ALU Immediate (I-type) //
////////////////////////////

/// Add immediate: `rd = rs1 + imm`.
pub fn addi(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_IMM, rd, rs1, F3_ADD, imm);
}

/// Set less than immediate (signed): `rd = (rs1 < imm) ? 1 : 0`.
pub fn slti(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_IMM, rd, rs1, F3_SLT, imm);
}

/// Set less than immediate unsigned: `rd = (rs1 < imm) ? 1 : 0`.
pub fn sltiu(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_IMM, rd, rs1, F3_SLTU, imm);
}

/// XOR immediate: `rd = rs1 ^ imm`.
pub fn xori(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_IMM, rd, rs1, F3_XOR, imm);
}

/// OR immediate: `rd = rs1 | imm`.
pub fn ori(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_IMM, rd, rs1, F3_OR, imm);
}

/// AND immediate: `rd = rs1 & imm`.
pub fn andi(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_IMM, rd, rs1, F3_AND, imm);
}

/// Shift left logical immediate: `rd = rs1 << shamt`.
pub fn slli(rd: super::Reg, rs1: super::Reg, shamt: i32) -> u32 {
    assert shamt >= 0 and shamt < 64;
    return encodeI(OP_IMM, rd, rs1, F3_SLL, shamt & 0x3F);
}

/// Shift right logical immediate: `rd = rs1 >> shamt` (zero-extend).
pub fn srli(rd: super::Reg, rs1: super::Reg, shamt: i32) -> u32 {
    assert shamt >= 0 and shamt < 64;
    return encodeI(OP_IMM, rd, rs1, F3_SRL, shamt & 0x3F);
}

/// Shift right arithmetic immediate: `rd = rs1 >> shamt` (sign-extend).
pub fn srai(rd: super::Reg, rs1: super::Reg, shamt: i32) -> u32 {
    assert shamt >= 0 and shamt < 64;
    // SRAI has bit 10 set in immediate field (becomes bit 30 in instruction)
    return encodeI(OP_IMM, rd, rs1, F3_SRL, (shamt & 0x3F) | 0b10000000000);
}

///////////////////////////
// ALU Register (R-type) //
///////////////////////////

/// Add: `rd = rs1 + rs2`.
pub fn add(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_ADD, F7_NORMAL);
}

/// Subtract: `rd = rs1 - rs2`.
pub fn sub(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_ADD, F7_SUB);
}

/// Shift left logical: `rd = rs1 << rs2[5:0]`.
pub fn sll(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_SLL, F7_NORMAL);
}

/// Set less than (signed): `rd = (rs1 < rs2) ? 1 : 0`.
pub fn slt(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_SLT, F7_NORMAL);
}

/// Set less than unsigned: `rd = (rs1 < rs2) ? 1 : 0`.
pub fn sltu(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_SLTU, F7_NORMAL);
}

/// XOR: `rd = rs1 ^ rs2`.
pub fn xor(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_XOR, F7_NORMAL);
}

/// Shift right logical: `rd = rs1 >> rs2[5:0]` (zero-extend).
pub fn srl(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_SRL, F7_NORMAL);
}

/// Shift right arithmetic: `rd = rs1 >> rs2[5:0]` (sign-extend).
pub fn sra(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_SRL, F7_SRA);
}

/// OR: `rd = rs1 | rs2`.
pub fn or_(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_OR, F7_NORMAL);
}

/// AND: `rd = rs1 & rs2`.
pub fn and_(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_AND, F7_NORMAL);
}

/////////////////
// M Extension //
/////////////////

/// Multiply: `rd = (rs1 * rs2)[63:0]`.
pub fn mul(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_ADD, F7_MUL);
}

/// Multiply high (signed x signed): `rd = (rs1 * rs2)[127:64]`.
pub fn mulh(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_SLL, F7_MUL);
}

/// Multiply high (signed x unsigned): `rd = (rs1 * rs2)[127:64]`.
pub fn mulhsu(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_SLT, F7_MUL);
}

/// Multiply high (unsigned x unsigned): `rd = (rs1 * rs2)[127:64]`.
pub fn mulhu(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_SLTU, F7_MUL);
}

/// Divide (signed): `rd = rs1 / rs2`.
pub fn div(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_XOR, F7_MUL);
}

/// Divide (unsigned): `rd = rs1 / rs2`.
pub fn divu(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_SRL, F7_MUL);
}

/// Remainder (signed): `rd = rs1 % rs2`.
pub fn rem(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_OR, F7_MUL);
}

/// Remainder (unsigned): `rd = rs1 % rs2`.
pub fn remu(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP, rd, rs1, rs2, F3_AND, F7_MUL);
}

//////////////////////////
// RV64 Word Operations //
//////////////////////////

/// Add immediate word (32-bit, sign-extended): `rd = sign_ext((rs1 + imm)[31:0])`.
pub fn addiw(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_IMM32, rd, rs1, F3_ADD, imm);
}

/// Shift left logical immediate word: `rd = sign_ext((rs1 << shamt)[31:0])`.
pub fn slliw(rd: super::Reg, rs1: super::Reg, shamt: i32) -> u32 {
    assert shamt >= 0 and shamt < 32;
    return encodeI(OP_IMM32, rd, rs1, F3_SLL, shamt & 0x1F);
}

/// Shift right logical immediate word: `rd = sign_ext((rs1[31:0] >> shamt))`.
pub fn srliw(rd: super::Reg, rs1: super::Reg, shamt: i32) -> u32 {
    assert shamt >= 0 and shamt < 32;
    return encodeI(OP_IMM32, rd, rs1, F3_SRL, shamt & 0x1F);
}

/// Shift right arithmetic immediate word: `rd = sign_ext((rs1[31:0] >> shamt))` (sign-extended).
pub fn sraiw(rd: super::Reg, rs1: super::Reg, shamt: i32) -> u32 {
    assert shamt >= 0 and shamt < 32;
    return encodeI(OP_IMM32, rd, rs1, F3_SRL, (shamt & 0x1F) | 0b10000000000);
}

/// Add word: `rd = sign_ext((rs1 + rs2)[31:0])`.
pub fn addw(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP32, rd, rs1, rs2, F3_ADD, F7_NORMAL);
}

/// Subtract word: `rd = sign_ext((rs1 - rs2)[31:0])`.
pub fn subw(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP32, rd, rs1, rs2, F3_ADD, F7_SUB);
}

/// Shift left logical word: `rd = sign_ext((rs1 << rs2[4:0])[31:0])`.
pub fn sllw(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP32, rd, rs1, rs2, F3_SLL, F7_NORMAL);
}

/// Shift right logical word: `rd = sign_ext((rs1[31:0] >> rs2[4:0]))`.
pub fn srlw(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP32, rd, rs1, rs2, F3_SRL, F7_NORMAL);
}

/// Shift right arithmetic word: `rd = sign_ext((rs1[31:0] >> rs2[4:0]))` (sign-extended).
pub fn sraw(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP32, rd, rs1, rs2, F3_SRL, F7_SRA);
}

/// Multiply word: `rd = sign_ext((rs1 * rs2)[31:0])`.
pub fn mulw(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP32, rd, rs1, rs2, F3_ADD, F7_MUL);
}

/// Divide word (signed): `rd = sign_ext(rs1[31:0] / rs2[31:0])`.
pub fn divw(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP32, rd, rs1, rs2, F3_XOR, F7_MUL);
}

/// Divide word (unsigned): `rd = sign_ext(rs1[31:0] / rs2[31:0])`.
pub fn divuw(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP32, rd, rs1, rs2, F3_SRL, F7_MUL);
}

/// Remainder word (signed): `rd = sign_ext(rs1[31:0] % rs2[31:0])`.
pub fn remw(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP32, rd, rs1, rs2, F3_OR, F7_MUL);
}

/// Remainder word (unsigned): `rd = sign_ext(rs1[31:0] % rs2[31:0])`.
pub fn remuw(rd: super::Reg, rs1: super::Reg, rs2: super::Reg) -> u32 {
    return encodeR(OP_OP32, rd, rs1, rs2, F3_AND, F7_MUL);
}

///////////////////
// Load (I-type) //
///////////////////

/// Load byte (sign-extend): `rd = mem[rs1 + imm][7:0]`.
pub fn lb(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_LOAD, rd, rs1, F3_BYTE, imm);
}

/// Load halfword (sign-extend): `rd = mem[rs1 + imm][15:0]`.
pub fn lh(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_LOAD, rd, rs1, F3_HALF, imm);
}

/// Load word (sign-extend to 64-bit): `rd = sign_ext(mem[rs1 + imm][31:0])`.
pub fn lw(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_LOAD, rd, rs1, F3_WORD, imm);
}

/// Load byte unsigned (zero-extend): `rd = mem[rs1 + imm][7:0]`.
pub fn lbu(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_LOAD, rd, rs1, F3_BYTE_U, imm);
}

/// Load halfword unsigned (zero-extend): `rd = mem[rs1 + imm][15:0]`.
pub fn lhu(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_LOAD, rd, rs1, F3_HALF_U, imm);
}

/// Load word unsigned (zero-extend to 64-bit): `rd = mem[rs1 + imm][31:0]`.
pub fn lwu(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_LOAD, rd, rs1, F3_WORD_U, imm);
}

/// Load doubleword: `rd = mem[rs1 + imm][63:0]`.
pub fn ld(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_LOAD, rd, rs1, F3_DWORD, imm);
}

////////////////////
// Store (S-type) //
////////////////////

/// Store byte: `mem[rs1 + imm] = rs2[7:0]`.
pub fn sb(rs2: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeS(OP_STORE, rs1, rs2, F3_BYTE, imm);
}

/// Store halfword: `mem[rs1 + imm] = rs2[15:0]`.
pub fn sh(rs2: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeS(OP_STORE, rs1, rs2, F3_HALF, imm);
}

/// Store word: `mem[rs1 + imm] = rs2[31:0]`.
pub fn sw(rs2: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeS(OP_STORE, rs1, rs2, F3_WORD, imm);
}

/// Store doubleword: `mem[rs1 + imm] = rs2[63:0]`.
pub fn sd(rs2: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeS(OP_STORE, rs1, rs2, F3_DWORD, imm);
}

/////////////////////
// Branch (B-type) //
/////////////////////

/// Branch if equal: `if (rs1 == rs2) pc += imm`.
pub fn beq(rs1: super::Reg, rs2: super::Reg, imm: i32) -> u32 {
    return encodeB(OP_BRANCH, rs1, rs2, F3_BEQ, imm);
}

/// Branch if not equal: `if (rs1 != rs2) pc += imm`.
pub fn bne(rs1: super::Reg, rs2: super::Reg, imm: i32) -> u32 {
    return encodeB(OP_BRANCH, rs1, rs2, F3_BNE, imm);
}

/// Branch if less than (signed): `if (rs1 < rs2) pc += imm`.
pub fn blt(rs1: super::Reg, rs2: super::Reg, imm: i32) -> u32 {
    return encodeB(OP_BRANCH, rs1, rs2, F3_BLT, imm);
}

/// Branch if greater or equal (signed): `if (rs1 >= rs2) pc += imm`.
pub fn bge(rs1: super::Reg, rs2: super::Reg, imm: i32) -> u32 {
    return encodeB(OP_BRANCH, rs1, rs2, F3_BGE, imm);
}

/// Branch if less than unsigned: `if (rs1 < rs2) pc += imm`.
pub fn bltu(rs1: super::Reg, rs2: super::Reg, imm: i32) -> u32 {
    return encodeB(OP_BRANCH, rs1, rs2, F3_BLTU, imm);
}

/// Branch if greater or equal unsigned: `if (rs1 >= rs2) pc += imm`.
pub fn bgeu(rs1: super::Reg, rs2: super::Reg, imm: i32) -> u32 {
    return encodeB(OP_BRANCH, rs1, rs2, F3_BGEU, imm);
}

//////////
// Jump //
//////////

/// Jump and link: `rd = pc + 4; pc += imm`.
pub fn jal(rd: super::Reg, imm: i32) -> u32 {
    return encodeJ(OP_JAL, rd, imm);
}

/// Jump and link register: `rd = pc + 4; pc = rs1 + imm`.
pub fn jalr(rd: super::Reg, rs1: super::Reg, imm: i32) -> u32 {
    return encodeI(OP_JALR, rd, rs1, 0, imm);
}

/////////////////////
// Upper Immediate //
/////////////////////

/// Load upper immediate: `rd = imm << 12`.
pub fn lui(rd: super::Reg, imm: i32) -> u32 {
    return encodeU(OP_LUI, rd, imm);
}

/// Add upper immediate to PC: `rd = pc + (imm << 12)`.
pub fn auipc(rd: super::Reg, imm: i32) -> u32 {
    return encodeU(OP_AUIPC, rd, imm);
}

////////////
// System //
////////////

/// Environment call (system call).
pub fn ecall() -> u32 {
    return encodeI(OP_SYSTEM, super::ZERO, super::ZERO, 0, 0);
}

/// Environment break (debugger breakpoint).
pub fn ebreak() -> u32 {
    return encodeI(OP_SYSTEM, super::ZERO, super::ZERO, 0, 1);
}

/////////////////////////
// Pseudo-instructions //
/////////////////////////

/// No operation: `addi zero, zero, 0`.
pub fn nop() -> u32 {
    return addi(super::ZERO, super::ZERO, 0);
}

/// Move: `rd = rs` (`addi rd, rs, 0`).
pub fn mv(rd: super::Reg, rs: super::Reg) -> u32 {
    return addi(rd, rs, 0);
}

/// Bitwise NOT: `rd = ~rs` (`xori rd, rs, -1`).
pub fn not_(rd: super::Reg, rs: super::Reg) -> u32 {
    return xori(rd, rs, -1);
}

/// Negate: `rd = -rs` (`sub rd, zero, rs`).
pub fn neg(rd: super::Reg, rs: super::Reg) -> u32 {
    return sub(rd, super::ZERO, rs);
}

/// Return: `jalr zero, ra, 0`.
pub fn ret() -> u32 {
    return jalr(super::ZERO, super::RA, 0);
}

/// Jump (unconditional): `jal zero, imm`.
pub fn j(imm: i32) -> u32 {
    return jal(super::ZERO, imm);
}

/// Branch if less than or equal (signed): `if (rs1 <= rs2) pc += imm`.
/// Implemented as `bge rs2, rs1, imm` (swap operands).
pub fn ble(rs1: super::Reg, rs2: super::Reg, imm: i32) -> u32 {
    return bge(rs2, rs1, imm);
}

/// Branch if greater than (signed): `if (rs1 > rs2) pc += imm`.
/// Implemented as `blt rs2, rs1, imm` (swap operands).
pub fn bgt(rs1: super::Reg, rs2: super::Reg, imm: i32) -> u32 {
    return blt(rs2, rs1, imm);
}

/// Branch if less than or equal unsigned: `if (rs1 <= rs2) pc += imm`.
/// Implemented as `bgeu rs2, rs1, imm` (swap operands).
pub fn bleu(rs1: super::Reg, rs2: super::Reg, imm: i32) -> u32 {
    return bgeu(rs2, rs1, imm);
}

/// Branch if greater than unsigned: `if (rs1 > rs2) pc += imm`.
/// Implemented as `bltu rs2, rs1, imm` (swap operands).
pub fn bgtu(rs1: super::Reg, rs2: super::Reg, imm: i32) -> u32 {
    return bltu(rs2, rs1, imm);
}

/// Set if equal to zero: `rd = (rs == 0) ? 1 : 0`.
/// Implemented as `sltiu rd, rs, 1`.
pub fn seqz(rd: super::Reg, rs: super::Reg) -> u32 {
    return sltiu(rd, rs, 1);
}

/// Set if not equal to zero: `rd = (rs != 0) ? 1 : 0`.
/// Implemented as `sltu rd, zero, rs`.
pub fn snez(rd: super::Reg, rs: super::Reg) -> u32 {
    return sltu(rd, super::ZERO, rs);
}

/// Branch if equal to zero: `if (rs == 0) pc += imm`.
pub fn beqz(rs: super::Reg, imm: i32) -> u32 {
    return beq(rs, super::ZERO, imm);
}

/// Branch if not equal to zero: `if (rs != 0) pc += imm`.
pub fn bnez(rs: super::Reg, imm: i32) -> u32 {
    return bne(rs, super::ZERO, imm);
}

/// Call: `jal ra, imm`.
pub fn call(imm: i32) -> u32 {
    return jal(super::RA, imm);
}