try emitBr(self, condReg, thenBlock, elseBlock);

}

/// Emit a 32-bit store instruction at the given offset.

    emit(self, il::Instr::Store { typ: il::Type::W32, src, dst, offset });

}

/// Emit a 32-bit load instruction at the given offset.

    emit(self, il::Instr::Load { typ: il::Type::W32, dst, src, offset });

}

/// Emit an 8-bit store instruction at the given offset.

    emit(self, il::Instr::Store { typ: il::Type::W8, src, dst, offset });

}

/// Emit an 8-bit load instruction at the given offset.

    emit(self, il::Instr::Load { typ: il::Type::W8, dst, src, offset });

}

/// Emit a 64-bit store instruction at the given offset.

    emit(self, il::Instr::Store { typ: il::Type::W64, src, dst, offset });

}

/// Emit a 64-bit load instruction at the given offset.

    emit(self, il::Instr::Load { typ: il::Type::W64, dst, src, offset });

}

/// Load a tag from memory at `src` plus `offset` with the given IL type.

    let dst = nextReg(self);

    emit(self, il::Instr::Load { typ: tagType, dst, src, offset });

    return il::Val::Reg(dst);

}

/// Load the data pointer from a slice value.

    let ptrReg = nextReg(self);

    emitLoadW64At(self, ptrReg, sliceReg, SLICE_PTR_OFFSET);

    return ptrReg;

}

/// Load the length from a slice value.

    let lenReg = nextReg(self);

    emitLoadW32At(self, lenReg, sliceReg, SLICE_LEN_OFFSET);

    return il::Val::Reg(lenReg);

}

/// Return a fixed array length or load the length from a slice value.

    self: &mut FnLowerer 'arena 'phase 'function,

    base: il::Reg,

    length: ?u32

) -> il::Val where 'arena: 'phase, 'phase: 'function {

    if let len = length { // Array (length is known).

    // Slice (length must be loaded).

    return loadSliceLen(self, base);

}

/// Load the capacity from a slice value.

    let capReg = nextReg(self);

    emitLoadW32At(self, capReg, sliceReg, SLICE_CAP_OFFSET);

    return il::Val::Reg(capReg);

}

        else => return false,

    }

}

/// Load the tag byte from a tagged value aggregate (optionals and unions).

    let tagReg = nextReg(self);

    emitLoadW8At(self, tagReg, base, TVAL_TAG_OFFSET);

    return tagReg;

}

/// Load the tag word from a result aggregate.

    let tagReg = nextReg(self);

    emitLoadW64At(self, tagReg, base, TVAL_TAG_OFFSET);

    return tagReg;

}

/// Get the register to compare against `0` for optional `nil` checking.

/// For null-ptr-optimized types, loads the data pointer, or returns it

/// directly for scalar pointers. For aggregates, returns the tag register.

    let reg = emitValToReg(self, val);

    match typ {

        case resolver::Type::Optional(resolver::Type::Slice { .. }) => {

            let ptrReg = nextReg(self);

    let layout = resolver::getTypeLayout(typ);

    return emitReserveLayout(self, layout);

}

/// Reserve stack storage with an explicit layout.

    let dst = nextReg(self);

    emit(self, il::Instr::Reserve {

        dst,

        size: il::Val::Imm(layout.size as i64),

    });

    return il::Val::Reg(slot);

}

/// Compute a field pointer by adding a byte offset to a base address.

    if offset == 0 {

        return base;

    }

    let dst = nextReg(self);

    return dst;

}

/// Emit an element address computation for array/slice indexing.

/// Computes: `base + idx * stride`.

    // If index is zero, return base directly.

    if idx == il::Val::Imm(0) {

        return base;

    }

    // If stride is `1`, skip the multiply.

    });

    return dst;

}

/// Emit a typed binary operation, returning the result as a value.

    let dst = nextReg(self);

    emit(self, il::Instr::BinOp { op, typ, dst, a, b });

    return il::Val::Reg(dst);

}

    let binOp = il::BinOp::Eq if op == ast::BinaryOp::Eq else il::BinOp::Ne;

    return emitTypedBinOp(self, binOp, il::Type::W8, tag, il::Val::Imm(tagIdx));

}

/// Logical "and" between two values. Returns the result in a register.

    let prev = left else {

        return right;

    };

    return emitTypedBinOp(self, il::BinOp::And, il::Type::W32, prev, right);

}

    try emitRetVal(self, resultVal);

}

/// Ensure a value is in a register (eg. for branch conditions).

    match val {

        case il::Val::Reg(r) => return r,

        case il::Val::Imm(_), il::Val::DataSym(_), il::Val::FnAddr(_) => {

            let dst = nextReg(self);

            emit(self, il::Instr::Copy { dst, val });