use std::mem;

use std::collections::dict;

use std::lang::il;

use std::lang::alloc;

use std::lang::gen::labels;

use std::lang::gen::regalloc;

use std::lang::gen::data;

use std::lang::gen::types;

////////////////

// Registers  //

////////////////

/// Create a register from a number. Panics if `n > 31`.

    assert n < 32;

}

////////////////////////////

// Architecture constants //

////////////////////////////

/////////////////////////

// Codegen Allocation  //

/////////////////////////

/// Argument registers for function calls.

/// Scratch register for code gen. Never allocated to user values.

/// Second scratch register for operations needing two temporaries.

/// Dedicated scratch for address offset adjustment. Never allocated to user

/// values and never used for operand materialization, so it can never

/// conflict with `rd`, `rs`, or `base` in load/store helpers.

/// Callee-saved registers that need save/restore if used.

/// Maximum 12-bit signed immediate value.

pub const MAX_IMM: i32 = 2047;

/// Minimum 12-bit signed immediate value.

pub const MIN_IMM: i32 = -2048;

];

/// Get target configuration for register allocation.

// TODO: This should be a constant variable.

pub fn targetConfig() -> regalloc::TargetConfig {

    return regalloc::TargetConfig {

        allocatable: &ALLOCATABLE_REGS[..],

        slotSize: DWORD_SIZE,

    };

}

///////////////////////

//! RV64 instruction decoder.

//!

//! Decodes 32-bit instruction words into structured representations.

use super::encode;

///////////////////////

// Field Extraction  //

///////////////////////

/////////////////////////

/// Decoded RV64 instruction.

pub union Instr {

    // R-type ALU.

    // R-type M extension.

    // R-type RV64 word operations.

    // I-type ALU.

    // I-type RV64 word immediate operations.

    // Load instructions.

    // Store instructions.

    // Branch instructions.

    // Jump instructions.

    // Upper immediate.

    // System.

    Ecall,

    Ebreak,

//!

//! Emits RV64 machine code as `u32` list.

use std::lang::il;

use std::lang::alloc;

use std::lang::gen::labels;

use std::lang::gen::types;

use std::collections::dict;

use std::mem;

}

/// Type of branch instruction.

pub union BranchKind {

    /// Conditional branch (B-type encoding).

    /// Inverted conditional branch (B-type encoding with negated condition).

    /// Unconditional jump (J-type encoding).

    Jump,

}

/// Function call that needs offset patching.

    /// Index in code buffer where the load was emitted.

    index: u32,

    /// Target function name.

    target: *[u8],

    /// Destination register.

}

/// Adjusted base register and offset for addressing.

pub record AdjustedOffset {

    /// Base register.

    /// Byte offset from register.

    offset: i32,

}

/// Callee-saved register with its stack offset.

pub record SavedReg {

    /// Register to save/restore.

    /// Offset from SP.

    offset: i32,

}

/// Emission context. Tracks state during code generation.

}

/// Record a function address load needing later patching.

/// Emits placeholder instructions that will be patched to load the function's address.

/// Uses two slots to compute long-distance addresses.

    assert e.pendingAddrLoadsLen < e.pendingAddrLoads.len, "recordAddrLoad: buffer full";

    e.pendingAddrLoads[e.pendingAddrLoadsLen] = PendingAddrLoad {

        index: e.codeLen,

        target,

        rd: rd,

    }

    e.pendingBranchesLen = 0;

}

/// Encode a conditional branch instruction.

    match op {

        case il::CmpOp::Eq => return encode::beq(rs1, rs2, offset),

        case il::CmpOp::Ne => return encode::bne(rs1, rs2, offset),

        case il::CmpOp::Slt => return encode::blt(rs1, rs2, offset),

        case il::CmpOp::Ult => return encode::bltu(rs1, rs2, offset),

    }

}

/// Encode an inverted conditional branch instruction.

    match op {

        case il::CmpOp::Eq => return encode::bne(rs1, rs2, offset),

        case il::CmpOp::Ne => return encode::beq(rs1, rs2, offset),

        case il::CmpOp::Slt => return encode::bge(rs1, rs2, offset),

        case il::CmpOp::Ult => return encode::bgeu(rs1, rs2, offset),

/// Adjust a large offset by loading *hi* bits into [`super::ADDR_SCRATCH`].

/// Returns adjusted base register and remaining offset.

///

/// When the offset fits a 12-bit signed immediate, returns it unchanged.

/// Otherwise uses [`super::ADDR_SCRATCH`] for the LUI+ADD decomposition.

    if offset >= super::MIN_IMM and offset <= super::MAX_IMM {

        return AdjustedOffset { base, offset };

    }

    let s = splitImm(offset);

    emit(e, encode::lui(super::ADDR_SCRATCH, s.hi));

/// Load an immediate value into a register.

/// Handles the full range of 64-bit immediates.

/// For values fitting in 12 bits, uses a single `ADDI`.

/// For values fitting in 32 bits, uses `LUI` + `ADDIW`.

/// For wider values, loads upper and lower halves then combines with shift and add.

    let immMin = super::MIN_IMM as i64;

    let immMax = super::MAX_IMM as i64;

    if imm >= immMin and imm <= immMax {

        emit(e, encode::addi(rd, super::ZERO, imm as i32));

    emit(e, encode::slli(rd, rd, 10));

    emit(e, encode::addi(rd, rd, lower & 0x3FF));

}

/// Emit add-immediate, handling large immediates.

    if imm >= super::MIN_IMM and imm <= super::MAX_IMM {

        emit(e, encode::addi(rd, rs, imm));

    } else {

        loadImm(e, super::SCRATCH1, imm as i64);

        emit(e, encode::add(rd, rs, super::SCRATCH1));

////////////////////////

// Load/Store Helpers //

////////////////////////

/// Emit unsigned load with automatic offset adjustment.

    let adj = adjustOffset(e, base, offset);

    match typ {

        case il::Type::W8 => emit(e, encode::lbu(rd, adj.base, adj.offset)),

        case il::Type::W16 => emit(e, encode::lhu(rd, adj.base, adj.offset)),

        case il::Type::W32 => emit(e, encode::lwu(rd, adj.base, adj.offset)),

        case il::Type::W64 => emit(e, encode::ld(rd, adj.base, adj.offset)),

    }

}

/// Emit signed load with automatic offset adjustment.

    let adj = adjustOffset(e, base, offset);

    match typ {

        case il::Type::W8 => emit(e, encode::lb(rd, adj.base, adj.offset)),

        case il::Type::W16 => emit(e, encode::lh(rd, adj.base, adj.offset)),

        case il::Type::W32 => emit(e, encode::lw(rd, adj.base, adj.offset)),

        case il::Type::W64 => emit(e, encode::ld(rd, adj.base, adj.offset)),

    }

}

/// Emit store with automatic offset adjustment.

    let adj = adjustOffset(e, base, offset);

    match typ {

        case il::Type::W8 => emit(e, encode::sb(rs, adj.base, adj.offset)),

        case il::Type::W16 => emit(e, encode::sh(rs, adj.base, adj.offset)),

        case il::Type::W32 => emit(e, encode::sw(rs, adj.base, adj.offset)),

        case il::Type::W64 => emit(e, encode::sd(rs, adj.base, adj.offset)),

    }

}

/// Emit 64-bit load with automatic offset adjustment.

    let adj = adjustOffset(e, base, offset);

    emit(e, encode::ld(rd, adj.base, adj.offset));

}

/// Emit 64-bit store with automatic offset adjustment.

    let adj = adjustOffset(e, base, offset);

    emit(e, encode::sd(rs, adj.base, adj.offset));

}

/// Emit 32-bit load with automatic offset adjustment.

    let adj = adjustOffset(e, base, offset);

    emit(e, encode::lw(rd, adj.base, adj.offset));

}

/// Emit 32-bit store with automatic offset adjustment.

    let adj = adjustOffset(e, base, offset);

    emit(e, encode::sw(rs, adj.base, adj.offset));

}

/// Emit 8-bit load with automatic offset adjustment.

    let adj = adjustOffset(e, base, offset);

    emit(e, encode::lb(rd, adj.base, adj.offset));

}

/// Emit 8-bit store with automatic offset adjustment.

    let adj = adjustOffset(e, base, offset);

    emit(e, encode::sb(rs, adj.base, adj.offset));

}

//////////////////////////

//! RISC-V RV64I+M instruction encoding.

//!

//! Provides type-safe functions for encoding RV64 instructions.

//////////////////////

// Opcode Constants //

//////////////////////

pub const OP_LOAD:   u32 = 0x03;

//////////////////////

// Format Encoders  //

//////////////////////

/// Encode an R-type instruction.

    return (opcode        & 0x7F)

         | ((funct3       & 0x07) << 12)

         | ((funct7       & 0x7F) << 25);

}

/// Encode an I-type instruction.

    assert isSmallImm(imm);

    return (opcode        & 0x7F)

         | ((funct3       & 0x07)  << 12)

         | ((imm as u32   & 0xFFF) << 20);

}

/// Encode an S-type instruction.

    assert isSmallImm(imm);

    return (opcode  & 0x7F)

}

/// Encode a B-type (branch) instruction.

    assert isBranchImm(imm);

    let imm11   = (imm as u32 >> 11) & 0x1;

    let imm4_1  = (imm as u32 >> 1)  & 0xF;

    let imm10_5 = (imm as u32 >> 5)  & 0x3F;

    return (opcode        &  0x7F)

         | (imm11         << 7)

         | (imm4_1        << 8)

         | ((funct3       & 0x07) << 12)

         | (imm10_5       << 25)

         | (imm12         << 31);

}

/// Encode a U-type instruction.

    return (opcode       & 0x7F)

         | ((imm as u32  & 0xFFFFF) << 12);

}

/// Encode a J-type (jump) instruction.

    assert isJumpImm(imm);

    let imm20    = (imm as u32 >> 20) & 0x1;

    let imm10_1  = (imm as u32 >> 1)  & 0x3FF;

    let imm11    = (imm as u32 >> 11) & 0x1;

    let imm19_12 = (imm as u32 >> 12) & 0xFF;

    return (opcode       & 0x7F)

         | (imm19_12     << 12)

         | (imm11        << 20)

         | (imm10_1      << 21)

         | (imm20        << 31);

}

////////////////////////////

// ALU Immediate (I-type) //

////////////////////////////

/// Add immediate: `rd = rs1 + imm`.

    return encodeI(OP_IMM, rd, rs1, F3_ADD, imm);

}

/// Set less than immediate (signed): `rd = (rs1 < imm) ? 1 : 0`.

    return encodeI(OP_IMM, rd, rs1, F3_SLT, imm);

}

/// Set less than immediate unsigned: `rd = (rs1 < imm) ? 1 : 0`.

    return encodeI(OP_IMM, rd, rs1, F3_SLTU, imm);

}

/// XOR immediate: `rd = rs1 ^ imm`.

    return encodeI(OP_IMM, rd, rs1, F3_XOR, imm);

}

/// OR immediate: `rd = rs1 | imm`.

    return encodeI(OP_IMM, rd, rs1, F3_OR, imm);

}

/// AND immediate: `rd = rs1 & imm`.

    return encodeI(OP_IMM, rd, rs1, F3_AND, imm);

}

/// Shift left logical immediate: `rd = rs1 << shamt`.

    assert shamt >= 0 and shamt < 64;

    return encodeI(OP_IMM, rd, rs1, F3_SLL, shamt & 0x3F);

}

/// Shift right logical immediate: `rd = rs1 >> shamt` (zero-extend).

    assert shamt >= 0 and shamt < 64;

    return encodeI(OP_IMM, rd, rs1, F3_SRL, shamt & 0x3F);

}

/// Shift right arithmetic immediate: `rd = rs1 >> shamt` (sign-extend).

    assert shamt >= 0 and shamt < 64;

    // SRAI has bit 10 set in immediate field (becomes bit 30 in instruction)

    return encodeI(OP_IMM, rd, rs1, F3_SRL, (shamt & 0x3F) | 0b10000000000);

}

///////////////////////////

// ALU Register (R-type) //

///////////////////////////

/// Add: `rd = rs1 + rs2`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_ADD, F7_NORMAL);

}

/// Subtract: `rd = rs1 - rs2`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_ADD, F7_SUB);

}

/// Shift left logical: `rd = rs1 << rs2[5:0]`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_SLL, F7_NORMAL);

}

/// Set less than (signed): `rd = (rs1 < rs2) ? 1 : 0`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_SLT, F7_NORMAL);

}

/// Set less than unsigned: `rd = (rs1 < rs2) ? 1 : 0`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_SLTU, F7_NORMAL);

}

/// XOR: `rd = rs1 ^ rs2`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_XOR, F7_NORMAL);

}

/// Shift right logical: `rd = rs1 >> rs2[5:0]` (zero-extend).

    return encodeR(OP_OP, rd, rs1, rs2, F3_SRL, F7_NORMAL);

}

/// Shift right arithmetic: `rd = rs1 >> rs2[5:0]` (sign-extend).

    return encodeR(OP_OP, rd, rs1, rs2, F3_SRL, F7_SRA);

}

/// OR: `rd = rs1 | rs2`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_OR, F7_NORMAL);

}

/// AND: `rd = rs1 & rs2`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_AND, F7_NORMAL);

}

/////////////////

// M Extension //

/////////////////

/// Multiply: `rd = (rs1 * rs2)[63:0]`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_ADD, F7_MUL);

}

/// Multiply high (signed x signed): `rd = (rs1 * rs2)[127:64]`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_SLL, F7_MUL);

}

/// Multiply high (signed x unsigned): `rd = (rs1 * rs2)[127:64]`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_SLT, F7_MUL);

}

/// Multiply high (unsigned x unsigned): `rd = (rs1 * rs2)[127:64]`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_SLTU, F7_MUL);

}

/// Divide (signed): `rd = rs1 / rs2`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_XOR, F7_MUL);

}

/// Divide (unsigned): `rd = rs1 / rs2`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_SRL, F7_MUL);

}

/// Remainder (signed): `rd = rs1 % rs2`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_OR, F7_MUL);

}

/// Remainder (unsigned): `rd = rs1 % rs2`.

    return encodeR(OP_OP, rd, rs1, rs2, F3_AND, F7_MUL);

}

//////////////////////////

// RV64 Word Operations //

//////////////////////////

/// Add immediate word (32-bit, sign-extended): `rd = sign_ext((rs1 + imm)[31:0])`.

    return encodeI(OP_IMM32, rd, rs1, F3_ADD, imm);

}

/// Shift left logical immediate word: `rd = sign_ext((rs1 << shamt)[31:0])`.

    assert shamt >= 0 and shamt < 32;

    return encodeI(OP_IMM32, rd, rs1, F3_SLL, shamt & 0x1F);

}

/// Shift right logical immediate word: `rd = sign_ext((rs1[31:0] >> shamt))`.

    assert shamt >= 0 and shamt < 32;

    return encodeI(OP_IMM32, rd, rs1, F3_SRL, shamt & 0x1F);

}

/// Shift right arithmetic immediate word: `rd = sign_ext((rs1[31:0] >> shamt))` (sign-extended).

    assert shamt >= 0 and shamt < 32;

    return encodeI(OP_IMM32, rd, rs1, F3_SRL, (shamt & 0x1F) | 0b10000000000);

}

/// Add word: `rd = sign_ext((rs1 + rs2)[31:0])`.

    return encodeR(OP_OP32, rd, rs1, rs2, F3_ADD, F7_NORMAL);

}

/// Subtract word: `rd = sign_ext((rs1 - rs2)[31:0])`.

    return encodeR(OP_OP32, rd, rs1, rs2, F3_ADD, F7_SUB);

}

/// Shift left logical word: `rd = sign_ext((rs1 << rs2[4:0])[31:0])`.

    return encodeR(OP_OP32, rd, rs1, rs2, F3_SLL, F7_NORMAL);

}

/// Shift right logical word: `rd = sign_ext((rs1[31:0] >> rs2[4:0]))`.

    return encodeR(OP_OP32, rd, rs1, rs2, F3_SRL, F7_NORMAL);

}

/// Shift right arithmetic word: `rd = sign_ext((rs1[31:0] >> rs2[4:0]))` (sign-extended).

    return encodeR(OP_OP32, rd, rs1, rs2, F3_SRL, F7_SRA);

}

/// Multiply word: `rd = sign_ext((rs1 * rs2)[31:0])`.

    return encodeR(OP_OP32, rd, rs1, rs2, F3_ADD, F7_MUL);

}

/// Divide word (signed): `rd = sign_ext(rs1[31:0] / rs2[31:0])`.

    return encodeR(OP_OP32, rd, rs1, rs2, F3_XOR, F7_MUL);

}

/// Divide word (unsigned): `rd = sign_ext(rs1[31:0] / rs2[31:0])`.

    return encodeR(OP_OP32, rd, rs1, rs2, F3_SRL, F7_MUL);

}

/// Remainder word (signed): `rd = sign_ext(rs1[31:0] % rs2[31:0])`.

    return encodeR(OP_OP32, rd, rs1, rs2, F3_OR, F7_MUL);

}

/// Remainder word (unsigned): `rd = sign_ext(rs1[31:0] % rs2[31:0])`.

    return encodeR(OP_OP32, rd, rs1, rs2, F3_AND, F7_MUL);

}

///////////////////

// Load (I-type) //

///////////////////

/// Load byte (sign-extend): `rd = mem[rs1 + imm][7:0]`.

    return encodeI(OP_LOAD, rd, rs1, F3_BYTE, imm);

}

/// Load halfword (sign-extend): `rd = mem[rs1 + imm][15:0]`.

    return encodeI(OP_LOAD, rd, rs1, F3_HALF, imm);

}

/// Load word (sign-extend to 64-bit): `rd = sign_ext(mem[rs1 + imm][31:0])`.

    return encodeI(OP_LOAD, rd, rs1, F3_WORD, imm);

}

/// Load byte unsigned (zero-extend): `rd = mem[rs1 + imm][7:0]`.

    return encodeI(OP_LOAD, rd, rs1, F3_BYTE_U, imm);

}

/// Load halfword unsigned (zero-extend): `rd = mem[rs1 + imm][15:0]`.

    return encodeI(OP_LOAD, rd, rs1, F3_HALF_U, imm);

}

/// Load word unsigned (zero-extend to 64-bit): `rd = mem[rs1 + imm][31:0]`.

    return encodeI(OP_LOAD, rd, rs1, F3_WORD_U, imm);

}

/// Load doubleword: `rd = mem[rs1 + imm][63:0]`.

    return encodeI(OP_LOAD, rd, rs1, F3_DWORD, imm);

}

////////////////////

// Store (S-type) //

////////////////////

/// Store byte: `mem[rs1 + imm] = rs2[7:0]`.

    return encodeS(OP_STORE, rs1, rs2, F3_BYTE, imm);

}

/// Store halfword: `mem[rs1 + imm] = rs2[15:0]`.

    return encodeS(OP_STORE, rs1, rs2, F3_HALF, imm);

}

/// Store word: `mem[rs1 + imm] = rs2[31:0]`.

    return encodeS(OP_STORE, rs1, rs2, F3_WORD, imm);

}

/// Store doubleword: `mem[rs1 + imm] = rs2[63:0]`.

    return encodeS(OP_STORE, rs1, rs2, F3_DWORD, imm);

}

/////////////////////

// Branch (B-type) //

/////////////////////

/// Branch if equal: `if (rs1 == rs2) pc += imm`.

    return encodeB(OP_BRANCH, rs1, rs2, F3_BEQ, imm);

}

/// Branch if not equal: `if (rs1 != rs2) pc += imm`.

    return encodeB(OP_BRANCH, rs1, rs2, F3_BNE, imm);

}

/// Branch if less than (signed): `if (rs1 < rs2) pc += imm`.

    return encodeB(OP_BRANCH, rs1, rs2, F3_BLT, imm);

}

/// Branch if greater or equal (signed): `if (rs1 >= rs2) pc += imm`.

    return encodeB(OP_BRANCH, rs1, rs2, F3_BGE, imm);

}

/// Branch if less than unsigned: `if (rs1 < rs2) pc += imm`.

    return encodeB(OP_BRANCH, rs1, rs2, F3_BLTU, imm);

}

/// Branch if greater or equal unsigned: `if (rs1 >= rs2) pc += imm`.

    return encodeB(OP_BRANCH, rs1, rs2, F3_BGEU, imm);

}

//////////

// Jump //

//////////

/// Jump and link: `rd = pc + 4; pc += imm`.

    return encodeJ(OP_JAL, rd, imm);

}

/// Jump and link register: `rd = pc + 4; pc = rs1 + imm`.

    return encodeI(OP_JALR, rd, rs1, 0, imm);

}

/////////////////////

// Upper Immediate //

/////////////////////

/// Load upper immediate: `rd = imm << 12`.

    return encodeU(OP_LUI, rd, imm);

}

/// Add upper immediate to PC: `rd = pc + (imm << 12)`.

    return encodeU(OP_AUIPC, rd, imm);

}

////////////

// System //

pub fn nop() -> u32 {

    return addi(super::ZERO, super::ZERO, 0);

}

/// Move: `rd = rs` (`addi rd, rs, 0`).

    return addi(rd, rs, 0);

}

/// Bitwise NOT: `rd = ~rs` (`xori rd, rs, -1`).

    return xori(rd, rs, -1);

}

/// Negate: `rd = -rs` (`sub rd, zero, rs`).

    return sub(rd, super::ZERO, rs);

}

/// Return: `jalr zero, ra, 0`.

pub fn ret() -> u32 {

    return jal(super::ZERO, imm);

}

/// Branch if less than or equal (signed): `if (rs1 <= rs2) pc += imm`.

/// Implemented as `bge rs2, rs1, imm` (swap operands).

    return bge(rs2, rs1, imm);

}

/// Branch if greater than (signed): `if (rs1 > rs2) pc += imm`.

/// Implemented as `blt rs2, rs1, imm` (swap operands).

    return blt(rs2, rs1, imm);

}

/// Set if equal to zero: `rd = (rs == 0) ? 1 : 0`.

/// Implemented as `sltiu rd, rs, 1`.

    return sltiu(rd, rs, 1);

}

/// Set if not equal to zero: `rd = (rs != 0) ? 1 : 0`.

/// Implemented as `sltu rd, zero, rs`.

    return sltu(rd, super::ZERO, rs);

}

/// Branch if equal to zero: `if (rs == 0) pc += imm`.

    return beq(rs, super::ZERO, imm);

}

/// Branch if not equal to zero: `if (rs != 0) pc += imm`.

    return bne(rs, super::ZERO, imm);

}

/// Call: `jal ra, imm`.

pub fn call(imm: i32) -> u32 {

//!     Force an [`il::Val`] into a specific register `rd`. Built on [`resolveVal`] + [`emitMv`].

//!     Used when the instruction requires the value in `rd` (e.g. `sub rd, rd, rs2`).

use std::mem;

use std::lang::il;

use std::lang::gen::regalloc;

use std::lang::gen::labels;

use std::lang::gen::data;

use super::encode;

/// A pending spill store to be flushed after instruction selection.

record PendingSpill {

    /// The SSA register that was spilled.

    ssa: il::Reg,

    /// The physical register holding the value to store.

}

////////////////////

// Selector State //

////////////////////

/////////////////////////

// Register Allocation //

/////////////////////////

/// Get the physical register for an already-allocated SSA register.

    let phys = s.ralloc.assignments[ssa.n] else {

        panic "getReg: spilled register has no physical assignment";

    };

}

/// Compute the offset for a spill slot.

/// When using FP (dynamic): offset from FP = `slot - totalSize`.

/// When using SP: offset from SP = `slot`.

    }

    return slot;

}

/// Get the base register for spill slot addressing (FP or SP).

    if s.isDynamic {

        return super::FP;

    }

    return super::SP;

}

/// Get the destination register for an SSA register.

/// If the register is spilled, records a pending spill and returns the scratch

/// register. The pending spill is auto-committed by [`selectBlock`] after each

/// instruction. If not spilled, returns the physical register.

    if let _ = regalloc::spill::spillSlot(&s.ralloc.spill, ssa) {

        s.pendingSpill = PendingSpill { ssa, rd: scratch };

        return scratch;

    }

    return getReg(s, ssa);

}

/// Get the source register for an SSA register.

/// If the register is spilled, loads the value from the spill slot into the

/// scratch register and returns it. Otherwise returns the physical register.

    if let slot = regalloc::spill::spillSlot(&s.ralloc.spill, ssa) {

        emit::emitLd(s.e, scratch, spillBase(s), spillOffset(s, slot));

        return scratch;

    }

    return getReg(s, ssa);

}

/// Resolve an IL value to the physical register holding it.

/// For non-spilled register values, returns the physical register directly.

/// For immediates, symbols, and spilled registers, materializes into `scratch`.

    match val {

        case il::Val::Reg(r) => {

            return getSrcReg(s, r, scratch);

        },

        case il::Val::Imm(imm) => {

    }

}

/// Load an IL value into a specific physical register.

/// Like [`resolveVal`], but ensures the value ends up in `rd`.

    let rs = resolveVal(s, rd, val);

    emitMv(s, rd, rs);

    return rd;

}

/// Emit a move instruction if source and destination differ.

        emit::emit(s.e, encode::mv(rd, rs));

    }

}

/// Emit zero-extension from a sub-word type to the full register width.

    match typ {

        case il::Type::W8 => emit::emit(e, encode::andi(rd, rs, MASK_W8)),

        case il::Type::W16 => {

            emit::emit(e, encode::slli(rd, rs, SHIFT_W16));

            emit::emit(e, encode::srli(rd, rd, SHIFT_W16));

        case il::Type::W64 => {}

    }

}

/// Emit sign-extension from a sub-word type to the full register width.

    match typ {

        case il::Type::W8 => {

            emit::emit(e, encode::slli(rd, rs, SHIFT_W8));

            emit::emit(e, encode::srai(rd, rd, SHIFT_W8));

        },

        case il::Type::W64 => {}

    }

}

/// Resolve a value, trap if zero (unless known non-zero), and return the register.

    let rs2 = resolveVal(s, super::SCRATCH2, b);

    let mut knownNonZero = false;

    if let case il::Val::Imm(imm) = b {

        knownNonZero = imm != 0;

    }

            if let slot = regalloc::spill::spillSlot(&ralloc.spill, param) {

                // Spilled parameter: store arg register to spill slot.

                emit::emitSd(s.e, argReg, spillBase(&s), spillOffset(&s, slot));

            } else if let assigned = ralloc.assignments[param.n] {

            }

        }

    }

    // Emit each block.

            // it does, advance the base registers by the accumulated

            // offset and reset to zero.

            while remaining >= super::DWORD_SIZE {

                if offset > super::MAX_IMM - super::DWORD_SIZE {

                    emit::emitAddImm(s.e, rsrc, rsrc, offset);

                        emit::emitAddImm(s.e, rdst, rdst, offset);

                    }

                    offset = 0;

                }

                if let off = srcReload {

                remaining -= super::DWORD_SIZE;

            }

            if remaining >= super::WORD_SIZE {

                if offset > super::MAX_IMM - super::WORD_SIZE {

                    emit::emitAddImm(s.e, rsrc, rsrc, offset);

                        emit::emitAddImm(s.e, rdst, rdst, offset);

                    }

                    offset = 0;

                }

                if let off = srcReload {

                remaining -= super::WORD_SIZE;

            }

            while remaining > 0 {

                if offset > super::MAX_IMM - 1 {