else =>

                    panic "selectInstr: invalid reserve operand",

            }

        },

        case il::Instr::Blit { dst, src, size } => {

            let bothSpilled = regalloc::spill::isSpilled(&s.ralloc.spill, dst)

                and regalloc::spill::isSpilled(&s.ralloc.spill, src);

            // When both are spilled, offsets must fit 12-bit immediates

            // since we can't advance base registers (they live in spill

            // slots, not real registers we can mutate).

                panic "selectInstr: blit both-spilled with large size";

            }

            // Resolve dst/src base registers.

            let mut rdst = super::SCRATCH2;

            } else {

                rdst = getSrcReg(s, dst, super::SCRATCH2);

                rsrc = getSrcReg(s, src, super::SCRATCH2);

            }

            let mut offset: i32 = 0;

            // Copy loop: 8 bytes, then 4 bytes, then 1 byte at a time.

            // Before each load/store pair, check whether the offset is

            // about to exceed the 12-bit signed immediate range. When

            // it does, advance the base registers by the accumulated

                remaining -= 1;

            }

            // Restore base registers if they were advanced (never happens

            // in the both-spilled case since size <= MAX_IMM).

            if not bothSpilled {

                if advanced != 0 {

                    emit::emitAddImm(s.e, rsrc, rsrc, 0 - advanced);

                    if rdst.n != rsrc.n {

                        emit::emitAddImm(s.e, rdst, rdst, 0 - advanced);

                    }

        dst: Reg,

        /// Byte offset from the base address.

        offset: i32

    },

    /// Copy memory region: `blit %dst %src <size>;`

    Blit {

        /// Destination address.

        dst: Reg,

        /// Source address.

        src: Reg,

        /// Size to copy in bytes.

    },

    /// Copy a value into a register: `copy %dst <val>;`.

    Copy { dst: Reg, val: Val },

    /////////////////////

        case Instr::Sload { src, .. } => f(src, ctx),

        case Instr::Store { src, dst, .. } => {

            withReg(src, f, ctx);

            f(dst, ctx);

        },

            f(dst, ctx);

            f(src, ctx);

        },

        case Instr::Copy { val, .. } =>

            withReg(val, f, ctx),

        case Instr::BinOp { a, b, .. } => {

            withReg(a, f, ctx);

            write(out, "blit ");

            writeReg(out, a, dst);

            write(out, " ");

            writeReg(out, a, src);

            write(out, " ");

        }

        case super::Instr::Copy { dst, val } => {

            write(out, "copy ");

            writeReg(out, a, dst);

            write(out, " ");

    if isAggregateType(typ) {

        let dst = emitPtrOffset(self, base, offset);

        let src = try emitValToReg(self, src);

        let layout = resolver::getTypeLayout(typ);

    } else {

        emit(self, il::Instr::Store {

            typ: ilType(self.low, typ),

            src,

            dst: base,

fn emitRetVal(self: *mut FnLowerer, val: il::Val) throws (LowerError) {

    if let retReg = self.returnReg {

        let src = try emitValToReg(self, val);

        let size = retBufSize(self);

        emit(self, il::Instr::Ret { val: il::Val::Reg(retReg) });

    } else if isSmallAggregate(*self.fnType.returnType) {

        let src = try emitValToReg(self, val);

        let dst = nextReg(self);

        let mergeBlock = try createBlock(self, "cond#merge");

        try switchToAndSeal(self, thenBlock);

        let thenVal = try emitValToReg(self, try lowerExpr(self, cond.thenExpr));

        try emitJmp(self, mergeBlock);

        try switchToAndSeal(self, elseBlock);

        let elseVal = try emitValToReg(self, try lowerExpr(self, cond.elseExpr));

        try emitJmp(self, mergeBlock);

        try switchToAndSeal(self, mergeBlock);

        return il::Val::Reg(dst);

        let dst = try emitReserveLayout(self, callerLayout);

        emitStoreW64At(self, il::Val::Reg(tagReg), dst, TVAL_TAG_OFFSET);

        let srcPayload = emitPtrOffset(self, base, RESULT_VAL_OFFSET);

        let dstPayload = emitPtrOffset(self, dst, RESULT_VAL_OFFSET);

        try emitRetVal(self, il::Val::Reg(dst));

    }

    // Switch to the merge block if one was created. If all paths diverged

            // mutable copy so that callers that assign through the

            // resulting pointer do not fault.

            if isAggregateType(type) {

                let layout = resolver::getTypeLayout(type);

                let dst = try emitReserveLayout(self, layout);

                return il::Val::Reg(dst);

            }

            return emitRead(self, src, 0, type);

        }