///

/// Called after each function.

///

/// Uses two-instruction sequences: short branches use `branch` and `nop`,

/// long branches use inverted branch  and `jal` or `auipc` and `jalr`.

    if e.error <> nil {

        return;

    }

    for i in 0..e.pendingBranchesLen {

        let p = e.pendingBranches[i];

/////////////////////////

// Register Allocation //

/////////////////////////

/// Get the physical register for an already-allocated SSA register.

    let phys = s.ralloc.assignments[ssa.n] else {

        panic "getReg: spilled register has no physical assignment";

    };

    return phys;

}

/// Get the destination register for an SSA register.

/// If the register is spilled, records a pending spill and returns the scratch

/// register. The pending spill is auto-committed by [`selectBlock`] after each

/// instruction. If not spilled, returns the physical register.

    if let _ = regalloc::spill::spillSlot(&s.ralloc.spill, ssa) {

        set s.pendingSpill = PendingSpill { ssa, rd: scratch };

        return scratch;

    }

    return getReg(s, ssa);

}

/// Get the source register for an SSA register.

/// If the register is spilled, loads the value from the spill slot into the

/// scratch register and returns it. Otherwise returns the physical register.

    if let slot = regalloc::spill::spillSlot(&s.ralloc.spill, ssa) {

        emit::emitLd(s.e, scratch, spillBase(s), spillOffset(s, slot));

        return scratch;

    }

    return getReg(s, ssa);

}

/// Resolve an IL value to the physical register holding it.

/// For non-spilled register values, returns the physical register directly.

/// For immediates, symbols, and spilled registers, materializes into `scratch`.

    match val {

        case il::Val::Reg(r) => {

            return getSrcReg(s, r, scratch);

        },

        case il::Val::Imm(imm) => {

    }

}

/// Load an IL value into a specific physical register.

/// Like [`resolveVal`], but ensures the value ends up in `rd`.

    let rs = resolveVal(s, rd, val);

    emitMv(s, rd, rs);

    return rd;

}

/// Emit a move instruction if source and destination differ.

    if *rd <> *rs {

        emit::emit(s.e, encode::mv(rd, rs));

    }

}

    }

}

/// Resolve a divisor in its declared width, trap if it becomes zero, and

/// return the canonicalized register.

    s: &mut Selector 'scratch 'selection,

    b: il::Val,

    typ: il::Type,

    signed: bool

) -> gen::Reg where 'scratch: 'selection {

                emit::emitReturn(s.e, frame);

            }

        },

        case il::Instr::Jmp { target, args } => {

            // Move arguments to target block's parameter registers.

            // Skip branch if target is the next block (fallthrough).

            if target <> blockIdx + 1 {

                emit::recordBranch(s.e, target, emit::BranchKind::Jump);

            }

        },

            // execution fall through.

            if thenArgs.len > 0 and elseArgs.len > 0 {

                panic "selectInstr: both `then` and `else` have block arguments";

            } else if thenArgs.len > 0 {

                emit::recordBranch(s.e, elseTarget, emit::BranchKind::InvertedCond { op, rs1, rs2 });

                // Skip trailing jump if then is the next block (fallthrough).

                if thenTarget <> blockIdx + 1 {

                    emit::recordBranch(s.e, thenTarget, emit::BranchKind::Jump);

                }

            } else if thenTarget == blockIdx + 1 and elseArgs.len == 0 {

                // Then is the next block and no else args: invert the

                // condition to branch to else and fall through to then.

                emit::recordBranch(s.e, elseTarget, emit::BranchKind::InvertedCond { op, rs1, rs2 });

            } else {

                emit::recordBranch(s.e, thenTarget, emit::BranchKind::Cond { op, rs1, rs2 });

                // Skip trailing jump if else is the next block (fallthrough).

                if elseTarget <> blockIdx + 1 {

                    emit::recordBranch(s.e, elseTarget, emit::BranchKind::Jump);

                }

            }

                    set s.nextSynthBlock = skip + 1;

                    emit::recordBranch(s.e, skip, emit::BranchKind::InvertedCond {

                        op: il::CmpOp::Eq, rs1, rs2: super::SCRATCH2,

                    });

                    emit::recordBranch(s.e, c.target, emit::BranchKind::Jump);

                    emit::recordBlock(s.e, skip);

                } else {

                    emit::recordBranch(s.e, c.target, emit::BranchKind::Cond {

                        op: il::CmpOp::Eq, rs1, rs2: super::SCRATCH2,

                    });

                }

            }

            // Fall through to default.

            emit::recordBranch(s.e, defaultTarget, emit::BranchKind::Jump);

        },

        case il::Instr::Unreachable => {

            emit::emit(s.e, encode::ebreak());

        },

    return false;

}

/// Select a binary ALU operation, dispatching to the appropriate

/// instruction pattern based on the operation kind and type.

    match op {

        case il::BinOp::Add => {

            if typ == il::Type::W32 {

                // Inline W32 ADD with immediate optimization.

                if let case il::Val::Imm(imm) = b {

            selectCmp(s, typ, rd, rs1, b, CmpOp::Ult, true, super::SCRATCH2),

    }

}

/// Select a unary ALU operation.

    match op {

        case il::UnOp::Neg => {

            if typ == il::Type::W32 {

                emit::emit(s.e, encode::subw(rd, super::ZERO, rs));

            } else {

            emit::emit(s.e, encode::not_(rd, rs)),

    }

}

/// Select binary operation with immediate optimization.

    // Try immediate optimization first.

    if let case il::Val::Imm(imm) = b {

        if encode::isSmallImm64(imm) {

            let simm = imm as i32;

            match op {

}

/// Select shift operation with immediate optimization.

/// For 32-bit operations, uses the `*w` variants that operate on the lower 32 bits

/// and sign-extend the result.

    let isW32: bool = typ == il::Type::W32;

    // Try immediate optimization first.

    if let case il::Val::Imm(shamt) = b {

        // Keep immediate forms only for encodable shift amounts.

/// 1. Identifies "ready" moves.

/// 2. Executes ready moves.

/// 3. Breaks cycles using scratch register.

///

/// Entries with `ZERO` destination are skipped, as they are handled by caller.

    let n: u32 = args.len;

    if n == 0 {

        return;

    }

    if n > MAX_BLOCK_ARGS {

/// Emit moves from block arguments to target block's parameter registers.

///

/// Handles spilled destinations directly, then delegates to [`emitParallelMoves`]

/// for the remaining register-to-register parallel move resolution. Edges that

/// would overwrite an unconsumed spill source are unsupported.

    if args.len == 0 {

        return;

    }

    if args.len > MAX_BLOCK_ARGS {

        set s.e.error = super::Error::Capacity;

        return;

    }

    // The parallel-move resolver only handles register destinations. Keep eager

    // stores for independent spill slots, but reject dependencies that would

    // require stack staging rather than silently miscompiling them.

    for arg, i in args {

            let mut changesSlot = true;

            if let case il::Val::Reg(src) = arg {

                if let srcSlot = regalloc::spill::spillSlot(&s.ralloc.spill, src) {

                    if srcSlot == dstSlot {

                        set changesSlot = false;

                for source, j in args {

                    if let case il::Val::Reg(src) = source {

                        if let sourceSlot = regalloc::spill::spillSlot(&s.ralloc.spill, src) {

                            if sourceSlot == dstSlot {

                                if let sourceDstSlot = regalloc::spill::spillSlot(

                                ) {

                                    assert sourceDstSlot == dstSlot or j < i,

                                        "emitBlockArgs: overlapping spilled block arguments are unsupported";

                                } else {

                                    panic "emitBlockArgs: overlapping spilled block arguments are unsupported";

    // Destination registers for each arg.

    // Zero means the destination is spilled or skipped.

    let mut dsts: [gen::Reg; MAX_BLOCK_ARGS] = [super::ZERO; MAX_BLOCK_ARGS];

    for arg, i in args {

        // Spilled destinations: store directly to spill slot.

        // These don't participate in the parallel move algorithm.

        if let slot = regalloc::spill::spillSlot(&s.ralloc.spill, param) {

            if let case il::Val::Undef = arg {

    }

    emitParallelMoves(s, &dsts[..], args);

}

/// Select a comparison with immediate optimization.

    s: &mut Selector 'scratch 'selection,

    typ: il::Type,

    rd: gen::Reg,

    rs1: gen::Reg,

    b: il::Val,

        emit::emit(s.e, encode::xori(rd, rd, 1));

    }

}

/// Resolve one live Device access before an ordered user-mode register instruction.

    s: &mut Selector 'scratch 'selection,

    typ: il::Type,

    handle: il::Val,

    offset: il::Val,

    value: il::Val,