export mod atomics;

@test mod atomicTests;

    /// Memory fence with optional predecessor and successor masks.

    Fence,

export constant INSTRUCTIONS: [InstructionEntry; 89] = [

    { name: "fence",  encoder: InstructionEncoder::Fence },

    { name: "fence.i", encoder: InstructionEncoder::NoOperand { enc: encode::fenceI } },

use std::arch::rv64::atomics;

    if let format = atomics::parse(name) {

        let rd = try parseRegister(a);

        let mut rs2 = rv64::ZERO;

        if format.operation <> 2 { set rs2 = try parseRegister(a); }

        let memory = try parseMemory(a);

        if memory.offset <> 0 { throw fail(a, "atomic memory offset must be zero"); }

        try emit::emitText(a, atomics::encode(atomics::Instruction { format, rd, rs1: memory.base, rs2 }));

        return;

    }

        case super::InstructionEncoder::Fence => return try parseFence(a),

/// Parse an access-class mask without duplicate fields.

unsafe fn parseFenceMask(a: &mut super::Assembler) -> u32 throws (super::Error) {

    if a.scan.current.kind == scanner::TokenKind::Number {

        let value = try parseValue(a);

        if value <> 0 { throw fail(a, "numeric fence mask must be zero"); }

        return 0;

    }

    let token = try expectToken(a, scanner::TokenKind::Ident, "expected fence access classes");

    let mut mask: u32 = 0;

    for ch in token.source {

        let mut bit: u32 = 0;

        match ch {

            case 'i' => { set bit = 8; }, case 'o' => { set bit = 4; },

            case 'r' => { set bit = 2; }, case 'w' => { set bit = 1; },

            else => throw failOnToken(token, "invalid fence access class"),

        }

        if (mask & bit) <> 0 { throw failOnToken(token, "duplicate fence access class"); }

        set mask |= bit;

    }

    return mask;

}

/// Parse a full memory fence or a pair of explicit access-class masks.

unsafe fn parseFence(a: &mut super::Assembler) throws (super::Error) {

    if a.scan.current.kind == scanner::TokenKind::Semicolon {

        try emit::emitText(a, encode::fence());

        return;

    }

    let predecessor = try parseFenceMask(a);

    let successor = try parseFenceMask(a);

    try emit::emitText(a, encode::fenceOrder(predecessor, successor));

}

    while let ch = current(s); char::isAlpha(ch) or char::isDigit(ch) or ch == '_' or ch == '.' {

//! RV64 A-extension and fence encoding checks.

use std::testing;

use std::lang::alloc;

use std::lang::strings;

use super::atomics;

use super::encode;

use super::decode;

use super::asm;

/// Assembler workspace for individual atomic instruction fixtures.

static MEMORY: [u8; 65536] = [0; 65536];

/// Interned fixture names.

unsafe static STRINGS: strings::Pool = strings::Pool { table: undefined, count: 0 };

/// Output storage for one assembled instruction.

static WORDS: [u32; 1] = [0; 1];

/// Exact unordered word encodings for a0, a1, and a2 operands.

@test fn encodings() throws (testing::TestError) {

    let operations: [u32; 11] = [0, 1, 2, 3, 4, 8, 12, 16, 20, 24, 28];

    let words: [u32; 11] = [

        0x00c5a52f, 0x08c5a52f, 0x1005a52f, 0x18c5a52f, 0x20c5a52f,

        0x40c5a52f, 0x60c5a52f, 0x80c5a52f, 0xa0c5a52f, 0xc0c5a52f, 0xe0c5a52f,

    ];

    for operation, i in &operations[..] {

        for wide in 0..2 {

            for order in 0..4 {

                let item = atomics::Instruction {

                    format: atomics::Format { operation, width: 2 + wide, order },

                    rd: super::A0, rs1: super::A1, rs2: super::ZERO if operation == 2 else super::A2,

                };

                let word = words[i] | (wide << 12) | (order << 25);

                try testing::expect(atomics::encode(item) == word);

                let decoded = atomics::decode(word) else { throw testing::TestError::Failed; };

                try testing::expect(decoded == item);

                let case decode::Instr::Atomic(instruction) = decode::decode(word) else { throw testing::TestError::Failed; };

                try testing::expect(instruction == item);

            }

        }

    }

}

/// Reject reserved opcodes, widths, LR sources, and malformed suffixes.

@test fn invalid() throws (testing::TestError) {

    for word in &[0x2805a52f, 0x00c5852f, 0x10c5a52f, 0x00c5a513] {

        try testing::expect(atomics::decode(word) == nil);

    }

    for name in &["lr", "lr.q", "lr.w.aq.rl", "sc.d.rl.aq", "amoswap.d.bad", "amoadd.wextra"] {

        try testing::expect(atomics::parse(name) == nil);

    }

    let format = atomics::parse("amoswap.d.aqrl") else { throw testing::TestError::Failed; };

    try testing::expect(format.operation == 1 and format.width == 3 and format.order == 3);

}

/// Assemble one instruction and return its exact word.

unsafe fn assemble(source: *[u8]) -> u32 throws (testing::TestError) {

    let mut arena = alloc::new(&mut MEMORY[..]);

    let words = &mut WORDS[..];

    let data: *mut [u8] = &mut [];

    let result = try asm::assemble(asm::scanner::SourceKind::String, source,

        &mut words[..], &mut data[..], &mut arena, &mut STRINGS, 0)

        catch { throw testing::TestError::Failed; };

    try testing::expect(result.text.len == 1);

    return result.text[0];

}

/// Check instruction suffix scanning and assembler operand order.

@test unsafe fn assembly() throws (testing::TestError) {

    try testing::expect((try assemble("amoadd.d.aqrl %a0 %a2 (%a1);")) == 0x06c5b52f);

    try testing::expect((try assemble("amoswap.w.aq %a0 %a2 0(%a1);")) == 0x0cc5a52f);

    try testing::expect((try assemble("lr.d.aq %a0 (%a1);")) == 0x1405b52f);

    try testing::expect((try assemble("sc.w.rl %a0 %a2 (%a1);")) == 0x1ac5a52f);

    try testing::expect((try assemble("fence.i;")) == 0x0000100f);

    try testing::expect((try assemble("fence iorw iorw;")) == 0x0ff0000f);

    try testing::expect((try assemble("fence r rw;")) == 0x0230000f);

    try testing::expect((try assemble("fence rw w;")) == 0x0310000f);

    try testing::expect((try assemble("fence 0 0;")) == 0x0000000f);

}

/// Decode fence classes and local instruction synchronization.

@test fn fences() throws (testing::TestError) {

    try testing::expect(encode::fenceI() == 0x0000100f);

    try testing::expect(decode::decode(encode::fenceI()) == decode::Instr::FenceI);

    let case decode::Instr::Fence { predecessor, successor } = decode::decode(encode::fenceOrder(15, 15))

        else { throw testing::TestError::Failed; };

    try testing::expect(predecessor == 15 and successor == 15);

    let case decode::Instr::Unknown { .. } = decode::decode(0x0000200f)

        else { throw testing::TestError::Failed; };

}

/// Reject invalid atomic operands and fence access classes.

@test unsafe fn invalidAssembly() throws (testing::TestError) {

    for source in &[

        "lr.w %a0 %a2 (%a1);", "sc.d %a0 %a2 8(%a1);",

        "amoadd.d.aq.aq %a0 %a2 (%a1);", "fence rr rw;", "fence rx rw;",

        "fence 1 rw;", "fence.i %a0;",

    ] {

        let mut arena = alloc::new(&mut MEMORY[..]);

        let words = &mut WORDS[..];

        let data: *mut [u8] = &mut [];

        let mut rejected = false;

        try asm::assemble(asm::scanner::SourceKind::String, source,

            &mut words[..], &mut data[..], &mut arena, &mut STRINGS, 0) catch {

            set rejected = true;

        };

        try testing::expect(rejected);

    }

}

//! RV64 atomic instruction fields and canonical assembly names.

use std::mem;

use std::lang::gen;

/// Atomic operation, width, and ordering fields.

export record Format: Copy {

    /// Five-bit operation code from the A extension.

    operation: u32,

    /// Memory width encoding: 2 for a word, 3 for a doubleword.

    width: u32,

    /// Ordering bits: 2 for acquire, 1 for release, 3 for both.

    order: u32,

}

/// Decoded atomic instruction operands.

export record Instruction: Copy {

    /// Operation and ordering fields.

    format: Format,

    /// Destination register.

    rd: gen::Reg,

    /// Address register.

    rs1: gen::Reg,

    /// Source value; zero for load-reserved.

    rs2: gen::Reg,

}

/// An architectural operation and its mnemonic stem.

record Operation: Copy {

    /// Mnemonic without width or ordering suffixes.

    name: *[u8],

    /// Five-bit instruction field.

    code: u32,

}

/// Operations shared by the 32-bit and 64-bit forms.

constant OPERATIONS: [Operation; 11] = [

    { name: "amoadd", code: 0 }, { name: "amoswap", code: 1 },

    { name: "lr", code: 2 }, { name: "sc", code: 3 },

    { name: "amoxor", code: 4 }, { name: "amoor", code: 8 },

    { name: "amoand", code: 12 }, { name: "amomin", code: 16 },

    { name: "amomax", code: 20 }, { name: "amominu", code: 24 },

    { name: "amomaxu", code: 28 },

];

/// Look up an operation's canonical mnemonic stem.

export fn name(code: u32) -> ?*[u8] {

    for operation in &OPERATIONS[..] { if operation.code == code { return operation.name; } }

    return nil;

}

/// Parse an atomic mnemonic with mandatory width and optional ordering suffix.

export fn parse(text: *[u8]) -> ?Format {

    for operation in &OPERATIONS[..] {

        let n = operation.name.len;

        if text.len < n + 2 or not mem::eq(&text[..n], operation.name) or text[n] <> '.' { continue; }

        let mut width: u32 = 2;

        if text[n + 1] == 'd' { set width = 3; }

        else if text[n + 1] <> 'w' { return nil; }

        let suffix = &text[n + 2..];

        let mut order: u32 = 0;

        if mem::eq(suffix, ".aq") { set order = 2; }

        else if mem::eq(suffix, ".rl") { set order = 1; }

        else if mem::eq(suffix, ".aqrl") { set order = 3; }

        else if suffix.len <> 0 { return nil; }

        return Format { operation: operation.code, width, order };

    }

    return nil;

}

/// Encode a validated atomic operation and register operands.

export fn encode(instruction: Instruction) -> u32 {

    let format = instruction.format;

    assert name(format.operation) <> nil and (format.width == 2 or format.width == 3) and format.order <= 3;

    assert format.operation <> 2 or instruction.rs2 == super::ZERO;

    return 0x2f | (*instruction.rd as u32 << 7) | (format.width << 12)

        | (*instruction.rs1 as u32 << 15) | (*instruction.rs2 as u32 << 20)

        | (format.order << 25) | (format.operation << 27);

}

/// Decode a supported atomic word and reject reserved width and LR fields.

export fn decode(word: u32) -> ?Instruction {

    let operation = word >> 27;

    let width = (word >> 12) & 7;

    let rs2 = super::reg(((word >> 20) & 31) as u8);

    if (word & 127) <> 0x2f or name(operation) == nil or (width <> 2 and width <> 3) { return nil; }

    if operation == 2 and rs2 <> super::ZERO { return nil; }

    return Instruction {

        format: Format { operation, width, order: (word >> 25) & 3 },

        rd: super::reg(((word >> 7) & 31) as u8), rs1: super::reg(((word >> 15) & 31) as u8), rs2,

    };

}

use super::atomics;

    /// Atomic memory operation.

    Atomic(atomics::Instruction),

    /// Memory and I/O ordering fence.

    Fence {

        /// Ordered preceding access classes.

        predecessor: u32,

        /// Ordered following access classes.

        successor: u32,

    },

    /// Local instruction-fetch synchronization.

    FenceI,

        case 0x2f => {

            if let atomic = atomics::decode(instr) { return Instr::Atomic(atomic); }

            return Instr::Unknown { bits: instr };

        },

        case 0x0f => {

            if instr == 0x100f { return Instr::FenceI; }

            if (instr & 0xf00fffff) == 0x0f {

                return Instr::Fence { predecessor: (instr >> 24) & 15, successor: (instr >> 20) & 15 };

            }

            return Instr::Unknown { bits: instr };

        },

    return fenceOrder(3, 3);

/// Order the specified predecessor and successor memory or I/O access classes.

/// Each mask uses I=8, O=4, R=2, W=1.

export fn fenceOrder(predecessor: u32, successor: u32) -> u32 {

    assert predecessor <= 15 and successor <= 15;

    return 0x0f | (predecessor << 24) | (successor << 20);

}

/// Synchronize subsequent instruction fetch on the executing hart.

export fn fenceI() -> u32 { return 0x0000100f; }

use super::atomics;

        case decode::Instr::Atomic(instruction) => {

            let stem = atomics::name(instruction.format.operation) else panic "invalid atomic operation";

            write(out, stem);

            write(out, ".w" if instruction.format.width == 2 else ".d");

            match instruction.format.order {

                case 1 => write(out, ".rl"), case 2 => write(out, ".aq"), case 3 => write(out, ".aqrl"),

                else => {},

            }

            write(out, " "); write(out, regNameR(instruction.rd)); write(out, ", ");

            if instruction.format.operation <> 2 { write(out, regNameR(instruction.rs2)); write(out, ", "); }

            write(out, "0("); write(out, regNameR(instruction.rs1)); write(out, ")");

        },

        case decode::Instr::Fence { predecessor, successor } => {

            write(out, "fence "); fenceMask(out, predecessor); write(out, ", "); fenceMask(out, successor);

        },

        case decode::Instr::FenceI => write(out, "fence.i"),

/// Print a memory-ordering mask in canonical order.

unsafe fn fenceMask(out: &mut sexpr::Output, mask: u32) {

    if mask == 0 { write(out, "0"); return; }

    if (mask & 8) <> 0 { write(out, "i"); }

    if (mask & 4) <> 0 { write(out, "o"); }

    if (mask & 2) <> 0 { write(out, "r"); }

    if (mask & 1) <> 0 { write(out, "w"); }

}

lib/std/arch/rv64/atomics.rad

lib/std/arch/rv64/atomicTests.rad